Silicon oxide insulator (SOI) semiconductor having selectively linked body

• US 5,994,738 A
• Filed: 01/05/1999
• Issued: 11/30/1999
• Est. Priority Date: 12/16/1997
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices SDN Berhad (Advanced Micro Devices, Inc.)
• Inventors: Wollesen, Donald
• Primary Examiner(s): Ngo , Ngan V.
• Application Number:
  US09/225,658
• Time in Patent Office: 329 Days
• Field of Search: 257/350, 257/351, 257/354, 257/349, 257/347
• US Class Current: 257/347
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/7317 Bipolar thin film transistors
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78615 with a body contact
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A silicon oxide insulator (SOI) device includes an SOI layer supported on a silicon substrate. A body region is disposed on the SOI layer, and the body region is characterized by a first conductivity type. Source and drain regions are juxtaposed with the body region, with the source and drain regions being characterized by a second conductivity type. A transition region is disposed near the body region above the SOI layer, and the conductivity type of the transition region is established to be the first conductivity type for suppressing floating body effects in the body region and the second conductivity type for isolating the body region. An ohmic connector contacts the transition region and is connected to a drain power supply when the source and drain are doped with N-type dopants. On the other hand, the power supply is a source power supply when the source and drain are doped with P-type dopants. SOI bipolar transistors, pinch resistors, and diodes, all incorporating transition regions, are also disclosed.

Claims

1. A semiconductor device, comprising:

at least a first silicon oxide insulator (SOI) transistor and a second SOI transistor, at least the first SOI transistor having a semiconductive body region; and

a semiconductive transition region between the first and second SOI transistors, the transition region having a first conductivity type and communicating with a power supply voltage source, the first conductivity type and the voltage source being selected to selectively isolate the first SOI transistor from the second transistor such that the body region of the first SOI transistor exhibits a floating effect, or to link the body region such that the body region does not exhibit a floating effect.

2. The semiconductor device of claim 1, further comprising an ohmic connector connecting the transition region to the voltage source.

3. The semiconductor device of claim 2, wherein the transition region includes a relatively highly doped region and a relatively lightly doped region, and the ohmic connector contacts the relatively highly doped region.

4. The semiconductor device of claim 2, wherein the first transistor includes source and drain regions having the first conductivity type, and the transition region isolates the first SOI transistor from the second SOI transistor and wherein the body of the first SOI transistor exhibits a floating effect.

5. The semiconductor device of claim 2, wherein the first transistor includes source and drain regions having a second conductivity type opposite the first conductivity type, and the transition region links the body region of the first SOI transistor with the voltage source such that the body of the first SOI transistor substantially does not exhibit a floating effect.

6. The semiconductor device of claim 2, wherein the first SOI transistor includes source and drain regions, the source and drain regions are doped with an N-type dopant, and the voltage source is a transistor drain voltage source.

7. The semiconductor device of claim 2, wherein the first SOI transistor includes source and drain regions, the source and drain regions are doped with a P-type dopant, and the voltage source is a transistor source voltage source.

8. The semiconductor device of claim 3, wherein the relatively highly doped region is doped to a value of about 10¹⁹ atoms per cubic centimeter to 10²¹ atoms per cubic centimeter, and the relatively lightly doped region is doped to a value of about 10¹⁴ atoms per cubic centimeter to 10¹⁸ atoms per cubic centimeter.

9. The semiconductor device of claim 2, wherein the first SOI transistor includes a gate, and the device further comprises a conductor interconnecting the gate and the transition region to establish a dynamic threshold metal oxide silicon (DTMOS) device.

10. The semiconductor device of claim 1, wherein the power supply voltage source outputs a variable voltage for establishing a biased metal oxide silicon (MOS) device.

18. The semiconductor device of claim 9, wherein the transition region includes a relatively highly doped region and a relatively lightly doped region, and the ohmic connector contacts the relatively highly doped region.

11. A silicon oxide insulator (SOI) device, comprising:

at least one SOI layer;

at least one silicon substrate supporting the SOI layer;

at least one body region on the SOI layer, the body region being characterized by a first conductivity type;

at least source and drain regions juxtaposed with the body region, the source and drain regions being characterized by a second conductivity type; and

at least one transition region disposed near the body region above the SOI layer, the transition region being characterized by a transition conductivity type, wherein the transition conductivity type is established to be the first conductivity type for suppressing floating body effects in the body region, the transition conductivity type being established to be the second conductivity type for isolating the body region.

12. The device of claim 11, further comprising an ohmic connector in electrical contact with the transition region.

13. The device of claim 12, wherein the transition region includes a relatively highly doped region and a relatively lightly doped region, and the ohmic connector contacts the relatively highly doped region.

14. The device of claim 12, further comprising a voltage source connected to the ohmic connector, the voltage source being established to be a transistor drain voltage source when the source and drain regions are doped with an N-type dopant, and wherein the voltage source is established to be a transistor source voltage source when the source and drain regions are doped with a P-type dopant.

15. The device of claim 13, wherein the relatively highly doped region is doped to a value of about 10¹⁹ atoms per cubic centimeter to 10²¹ atoms per cubic centimeter, and the relatively lightly doped region is doped to a value of about 10¹⁴ atoms per cubic centimeter to 10¹⁸ atoms per cubic centimeter.

16. The device of claim 11, further comprising:

a gate; and

a conductor interconnecting the gate and the transition region to establish a dynamic threshold metal oxide silicon (DTMOS) device.

17. The device of claim 14, wherein the voltage source outputs a variable voltage for establishing a biased metal oxide silicon (MOS) device.

19. The device of claim 16, wherein the transition region includes a relatively highly doped region and a relatively lightly doped region, and the ohmic connector contacts the relatively highly doped region.