Memory cell configuration and method for its fabrication
First Claim
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1. A memory cell configuration, comprising:
- a semiconductor substrate having a main surface;
a plurality of webs disposed on and projecting above said main surface of said semiconductor substrate;
each of said webs being formed of a stack of doped layers with mutually adjacent layers having respectively opposite conductivity type doping, said stack having sidewalls;
three adjacent doped layers forming two source/drain regions and a channel region of a transistor;
a gate dielectric disposed on at least one sidewall of said stacks;
word lines running transversely to said webs and adjoining said gate dielectric at said sidewalls of said stacks;
bit lines formed by said doped layers acting as said source/drain regions;
said stack containing a number of doped layers sufficient to form at least two transistors disposed one above the other and connected in series via a common doped layer defining a common source/drain region.
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Abstract
The memory cell has transistors that are arranged three-dimensionally. Vertical MOS transistors are arranged on the sidewalls of semiconductor webs, and a plurality of transistors are arranged one above the other on each sidewall. The transistors that are arranged one above the other on a sidewall are connected in series.
143 Citations
13 Claims
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1. A memory cell configuration, comprising:
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a semiconductor substrate having a main surface; a plurality of webs disposed on and projecting above said main surface of said semiconductor substrate; each of said webs being formed of a stack of doped layers with mutually adjacent layers having respectively opposite conductivity type doping, said stack having sidewalls; three adjacent doped layers forming two source/drain regions and a channel region of a transistor; a gate dielectric disposed on at least one sidewall of said stacks; word lines running transversely to said webs and adjoining said gate dielectric at said sidewalls of said stacks; bit lines formed by said doped layers acting as said source/drain regions; said stack containing a number of doped layers sufficient to form at least two transistors disposed one above the other and connected in series via a common doped layer defining a common source/drain region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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Specification