Portable electronic data carrier

• US 5,994,770 A
• Filed: 04/24/1997
• Issued: 11/30/1999
• Est. Priority Date: 07/09/1991
• Status: Expired due to Fees

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Dallas Semiconductor Corporation (Analog Devices, Inc.)
• Inventors: Kurkowski, Hal, Cusey, James P., Harrington, Bradley M.
• Primary Examiner(s): LANE, JOHN A
• Application Number:
  US08/847,533
• Time in Patent Office: 950 Days
• Field of Search: 257/678, 257/679, 257/699, 257/700, 257/709, 257/710, 257/708, 257/729, 235/492
• US Class Current: 257/679
• CPC Class Codes: G01K 1/028 arrangements for numerical indication
• CPC Class Codes: G01K 7/245 in an oscillator circuit
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 21/73 by creating or determining hardware identification, e.g. serial numbers
• CPC Class Codes: G06K 19/07 with integrated circuit chips
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: G11C 8/20 Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access

Abstract

An apparatus includes a circuit positioned in a housing, which circuit includes an input/output module having a parasitic power sub-module. The circuit further includes a scratchpad memory, coupled to the input/output module; a programmable memory, coupled to the scratchpad memory; and a control module, coupled to the input/output module, the scratchpad memory and the programmable memory. In certain variations, the input/output module further includes at least one of a one-wire bus and a three-wire bus in addition to a bus arbitrator.

Claims

1. An apparatus comprising:

a circuit disposed in a housing, said housing having a cavity and formed from two substantially concave, electrically conductive surfaces with an insulating member disposed therebetween, said circuit comprising

an input/output module, said input/output module further comprising a parasitic power sub-module;

a scratchpad memory, coupled to said input/output module;

a programmable memory, coupled to said scratchpad memory; and

a control module, said control module coupled to said input/output module, said scratchpad memory and said programmable memory.

2. The apparatus of claim 1, wherein said control module further comprises:

verification means for verifying at least one of a data and an address.

3. The apparatus of claim 1, wherein said control module transfers a data block between said scratchpad memory and said programmable memory in response to a data block transfer command received by said input/output module.

4. The apparatus of claim 1, wherein said programmable memory comprises a plurality of memory blocks, each of said plurality of memory blocks being coupled to said scratchpad memory and said control module.

5. The apparatus of claim 1, wherein said plurality of memory blocks comprises at least four memory blocks.

6. The apparatus of claim 1, wherein said circuit further comprising:

accepting means to accept an intermittent voltage signal, applied between said two electrically conductive surfaces.

7. The apparatus of claim 1, wherein said parasitic power sub-module comprises:

at least one capacitor for storing energy from an intermittent voltage signal, applied between said two electrically conductive surfaces.

8. The apparatus of claim 1, wherein said circuit further comprises:

a voltage level detector coupled to said two electrically conductive surfaces, said voltage level detector detecting a voltage difference therebetween; and

a switch, coupled to said two electrically conductive surfaces, said switch controlling transmission of a signal by changing a resistance therebetween.

9. The apparatus of claim 1, wherein said input/output module, said scratchpad memory, said programmable memory and said control module are integrated as a monolithic circuit.

10. The apparatus of claim 1, wherein said housing is mountable to at least one physical item, said physical item selected from the group consisting of maintenance records, retail products, inventory, work-in-progress, machinery, cards, identification badges and any combination thereof.

11. The apparatus of claim 1, wherein said input/output module, said scratchpad memory, said programmable memory and said control module are packaged in a low-height package.

12. The apparatus of claim 11, wherein said low-height package is selected from the group consisting of a flat pack, a small out-line integrated circuit and any combination thereof.

13. The apparatus of claim 1, wherein said input/output module, said scratchpad memory, said programmable memory and said control module are combined into an integrated circuit, said integrated circuit mounted on a printed circuit board.

14. The apparatus of claim 1, wherein said housing is button-shaped, being approximately 6 millimeters in diameter and approximately 3 millimeters in thickness.

15. The apparatus of claim 1, wherein said input/output module further comprises a serial port and a program port.

16. The apparatus of claim 1, wherein said programmable memory comprises at least 1024 bits.

17. The apparatus of claim 1, further comprising:

a bus master module coupled to said input/output module, whereby said bus master module controls data communication between an external host and said input/output module.

18. The apparatus of claim 17, wherein said bus master module holds a data line to a first voltage level for a first time period, creates a transition between said first voltage level and a second voltage level, holds the data line at said second voltage level for a second time period, and interrogates said data line at a sample time to determine a data value.

19. The apparatus of claim 18, wherein said first time period is at least one microsecond.

20. The apparatus of claim 18, wherein said first voltage level is approximately five volts and corresponds to a logic high signal.

21. The apparatus of claim 18, wherein said second voltage level is selected from a zero volt and ground, and wherein said selected voltage level corresponds to a logic low signal.

22. The apparatus of claim 18, wherein said transition provides a reference time for said control module to coordinate a plurality of operations.

23. The apparatus of claim 18, wherein said second time period is at least one microsecond.

24. The apparatus of claim 18, wherein said sample time is at least 30 microseconds from said transition.

25. The apparatus of claim 1, further comprising a voltage level detector, coupled to said two electrically conductive surfaces, said voltage level detector detecting a voltage difference, said voltage difference used for programming said programmable memory.

26. The apparatus of claim 1, wherein said programmable memory comprises at least one memory cell, said at least one memory cell further comprising at least one field effect transistor, said at least one field effect transistor being programmed by a programming voltage signal received by said input/output module.

27. The apparatus of claim 1, wherein said input/output module comprises a voltage switch, said voltage switch being capable of detecting a voltage difference received at said input/output module, said voltage switch taking an action in response to said voltage difference, said action being dependent upon at least one of a data verification and an address verification, said action further being one of reading a value from said programmable memory or programming a location in said programmable memory.

28. The apparatus of claim 1, wherein said programmable memory comprises:

a read only memory.

29. The apparatus of claim 1, wherein said scratchpad memory comprises at least 8 bits.

30. An apparatus comprising:

a housing; and

a circuit disposed in said housing, said housing including a cavity and formed from two substantially concave, electrically conductive surfaces with an insulating member disposed therebetween, said circuit comprising;

an input/output module, said input/output module further comprising at least a bus having one-wire, said input/output module further comprising a bus arbitrator and a parasitic power sub-module;

a scratchpad memory, coupled to said input/output module;

a programmable memory, coupled to said scratchpad memory; and

a control module, said control module coupled to said input/output module, said scratchpad memory and said programmable memory.