Variable delay cell with a self-biasing load
First Claim
1. An apparatus comprising:
- an active side including a self-biasing load coupled to a differential pair coupled to a first biasing transistor, the active side providing a differential output;
an inactive side; and
a current steering circuit coupled between the active side and the inactive side to steer an amount of current drawn through each side responsive to a differential control input.
7 Assignments
0 Petitions
Accused Products
Abstract
A variable delay cell with a self-biasing load suitable for the implementation of a voltage controlled oscillator and other functions. Because the invention employs current steering between symmetric loads and fully differential voltage control, it is very fast relative to conventional methods and has reduced jitter and improved power supply noise rejection. Additionally, since the load is self-biasing, the need to externally generate a bias current for the load is eliminated. This significantly simplifies design. Also as the load readily self biases in response to changes in the bias current of the biasing transistor, desirable functionalities can be achieved merely by appropriately changing the bias current into the biasing transistor. Notably, the slew rate of both the rising and falling edge can be controlled in this way. Because the load provides a fully differential output, noise immunity as well as a 50% duty cycle is readily achieved.
98 Citations
20 Claims
-
1. An apparatus comprising:
-
an active side including a self-biasing load coupled to a differential pair coupled to a first biasing transistor, the active side providing a differential output; an inactive side; and a current steering circuit coupled between the active side and the inactive side to steer an amount of current drawn through each side responsive to a differential control input. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
-
-
12. A method comprising the steps of:
-
providing an active side and an inactive side of a delay cell, both sides having a self-biasing load; and steering current through one of the active side and the inactive side responsive to a differential control signal. - View Dependent Claims (13, 14)
-
-
15. A system comprising:
-
a serial bus; a first node and a second node coupled to the serial bus, the first node operating in a first clock domain; and a clock recovery circuit (CRC) within the first node to synchronize the first clock domain with the second clock domain, the CRC comprising a variable delay cell having an active side an inactive side and a current steering circuit the current steering circuit coupled between the active side and the inactive side to steer an amount of current drawn through each side responsive to a differential control input. - View Dependent Claims (16, 17, 18, 19, 20)
-
Specification