Apparatus and method for a combination D/A converter and FIR filter employing active current division from a single current source

• US 5,995,030 A
• Filed: 09/12/1995
• Issued: 11/30/1999
• Est. Priority Date: 02/16/1995
• Status: Expired due to Term

• Current Assignee: Microsemi Semiconductor (U.S.) Inc. (Microchip Technology Incorporated)
• Original Assignee: Advanced Micro Devices SDN Berhad (Advanced Micro Devices, Inc.)
• Inventors: Cabler, Carlin Dru
• Primary Examiner(s): Williams, Howard L.
• Application Number:
  US08/526,834
• Time in Patent Office: 1,540 Days
• Field of Search: 341/143, 341/144, 341/152, 377/42, 377/48, 377/76
• US Class Current: 341/143
• CPC Class Codes: H03H 17/0289 Digital and active filter structures
• CPC Class Codes: H03M 1/745 with weighted currents
• CPC Class Codes: H03M 3/504 the final digital/analogue converter being constituted by a finite impulse response [FIR] filter, i.e. FIRDAC

Abstract

An active current steering semi-digital FIR filter for a digital-to-analog conversion circuit, which includes a shift register having a 1-bit digital input stream and a plurality of output taps, where each output tap provides a 1-bit signal which has a value of a logic 1 or a logic 0, and a plurality of current paths, where each path includes an active element, such as a transistor, having a relatively high output impedance, which is connected to a common current source, and to an op amp for current-to-voltage conversion. The relatively high output impedance of the active current steering element causes any error term resulting from offset at the op amp inputs to be minimized.

Claims

1. An FIR filter for a digital-to-analog conversion circuit, comprising:

(a) a shift register having a 1-bit digital input stream and a plurality of output taps, wherein each said output tap provides a 1-bit signal which has a value of a logic 1 or a logic 0;

(b) a single current source having a current output divided by a plurality of current paths, wherein each said path includes an active element having a high output impedance, each said active element being connected to a first terminal of an active high switch and a first terminal of an active low switch;

wherein a single said output tap of said shift register is used to control said active high switch and said active low switch for a single current path; and

wherein a second terminal of each said active high switch of each of said plurality of current paths is connected to a non-inverted output current path, and a second terminal of each said active low switch for each of said plurality of current paths is connected to an inverted output current path.

2. The filter of claim 1, wherein said 1-bit digital input stream is output from an oversampled sigma-delta converter circuit.

3. The filter of claim 2, wherein said sigma-delta converter circuit comprises a digital interpolation circuit and a noise shaping circuit, wherein the output from said noise shaping circuit comprises said 1-bit digital input stream input to said shift register of said FIR filter.

4. The filter of claim 1, further comprising a differential current-to-voltage conversion circuit, comprising:

a first operational amplifier circuit having an input connected to said non-inverted current path and a first feedback resistor connected between said first op amp input and a first op amp output; and

a second operational amplifier circuit having an input connected to said inverted current path and a second feedback resistor connected between said second op amp input and a second op amp output;

wherein the voltage output from said first and said second op amp outputs comprises a differential output voltage.

5. The filter of claim 4, further comprising a means for converting said differential output voltage to a single-ended voltage.

6. The filter of claim 5, wherein said means for converting comprises a third operational amplifier, having a negative and a positive input terminal;

wherein said negative input terminal is connected to a third feedback resistor and to a series input resistor;

wherein said positive input terminal is connected to a voltage divider resistor network; and

wherein said series input resistor is also connected to said output of said first operational amplifier circuit and said voltage divider resistor network is also connected to said output of said second operational amplifier circuit.

7. The filter of claim 4, further comprising a first high frequency feedback capacitor connected in parallel with said first feedback resistor and a second high frequency feedback capacitor is connected in parallel with said second feedback resistor.

8. The filter of claim 1, wherein at least one of said active elements comprises a transistor.

9. The filter of claim 1, wherein at least one of said active elements comprises a MOS transistor biased in the saturation region.

10. The filter of claim 1, further comprising a DC offset current source connected to said inverted output current path and to said non-inverted output current path.

11. A method of converting a 1-bit digital input signal to an analog output signal, comprising the steps of:

(a) inputting said 1-bit digital input signal to a shift register;

(b) shifting said 1-bit signal through said shift register;

(c) providing, as a control bit, said shifted 1-bit signal to a plurality of output taps disposed along said shift register, wherein said control bit has a value of either a logic 1 or a logic 0;

(d) controlling a plurality of non-inverted current switches and inverted current switches with said bit-values of said shift register output taps, wherein a single output tap value controls a single pair of switches comprised of a single non-inverted current switch and a single inverted current switch, and wherein said plurality of non-inverted current switches and inverted current switches are connected to a common current source;

(e) producing a differential current from said plurality of non-inverting current switches and inverting current switches; and

(f) inputting said differential current to a first and a second op amp circuit, wherein a differential voltage is output from said first and second op amp circuits.

12. The method of claim 11, wherein said 1-bit digital input signal input to said shift register is output from an oversampled sigma-delta converter circuit.

13. The method of claim 12, wherein said sigma-delta converter circuit comprises a digital interpolation circuit and a noise shaping circuit, wherein said 1-bit digital signal input to said shift register is output from said noise shaping circuit.

14. The method of claim 11, wherein said first and second op amp circuits each include a feedback resister.

15. The method of claim 11, wherein said first and second op amp circuits each include a high frequency feedback capacitor.

16. The method of claim 11, further comprising the step of using a DC offset current source connected to said differential current to subtract a DC offset current value from said differential current.

17. The method of claim 11, further comprising the step of providing said differential voltage output from said first and second op amp circuits to a third op amp circuit which provides a single-ended output voltage.

18. The method of claim 17, wherein said third op amp circuit includes a series resistor connected to a first input of said third op amp circuit and a voltage divider resistor network connected to a second input of said third op amp circuit.

19. The method of claim 11, wherein each of said plurality of non-inverted current switches and inverted current switches are connected to said common current source through an active element.

20. The method of claim 19, wherein said active element comprises a transistor.

21. The method of claim 19, wherein said active element comprises a MOS transistor biased in the saturation region.

22. A method of converting a 1-bit digital input signal to an analog output signal, comprising the steps of:

(a) inputting said 1-bit digital input signal to a shift register;

(b) shifting said 1-bit signal through said shift register;

(c) providing, as a control bit, said shifted 1-bit signal to a plurality of output taps disposed along said shift register, wherein said control bit has a value of either a logic 1 or a logic 0;

(d) producing a differential current at a pair of current summing nodes by using said control bits to open or close switches disposed along a plurality of current paths connected to a common reference current source, wherein a DC offset current is subtracted from said differential current; and

(e) inputting said differential current to a current-to-voltage conversion circuit, wherein a differential voltage is output from said current-to-voltage conversion circuit.

23. The method of claim 22, wherein said DC offset current is equal to one-half the value of said common reference current source.