Plate line segmentation in a 1T/1C ferroelectric memory

• US 5,995,406 A
• Filed: 11/14/1997
• Issued: 11/30/1999
• Est. Priority Date: 11/14/1997
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Ramtron International Corporation (Infineon Technologies AG)
• Inventors: Lehman, Lark E., Kraus, William F.
• Primary Examiner(s): Dinh, Son T.
• Application Number:
  US08/970,448
• Time in Patent Office: 746 Days
• Field of Search: 365/145, 365/149, 365/230.03
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements

Abstract

A plate line segmentation scheme for a 1T/1C ferroelectric memory architecture includes an array of 1T/1C ferroelectric memory cells, word lines corresponding to each row of 1T/1C ferroelectric memory cells, and plate lines corresponding to each row of 1T/1C ferroelectric memory cells, wherein each plate line is divided into two or more equal plate line segments, only one of which is driven when a corresponding word line is selected.

Claims

1. A plate line segmentation scheme for a 1T/1C ferroelectric memory comprising:

a plurality of rows of 1T/1C ferroelectric memory cells;

a plurality of word lines corresponding to each row of 1T/1C ferroelectric memory cells; and

a plurality of plate lines corresponding to each row of 1T/1C ferroelectric memory cells, each plate line being divided into two or more plate line segments, only one of which is driven when a corresponding word line is selected.

2. A plate line segmentation scheme as in claim 1 in which each plate line is divided into four equal plate line segments.

3. A plate line segmentation scheme as in claim 1 in which each word line is coupled to 256 columns of ferroelectric memory cells and each plate line segment is coupled to 64 columns of ferroelectric memory cells.

4. A plate line segmentation scheme as in claim 1 further comprising a bank of sense amplifiers corresponding to each plate line segment.

5. A plate line segmentation scheme as in claim 4 in which only one bank of sense amplifiers is enabled corresponding to the driven plate line segment.

6. A plate line segmentation scheme as in claim 1 further comprising a bank of pre-charge circuits corresponding to each plate line segment.

7. A plate line segmentation scheme as in claim 6 in which only one bank of pre-charge circuits are disabled corresponding to the driven plate line segment.

8. A plate line segmentation scheme as in claim 1 further comprising a plurality of plate line driver circuits for selectively driving each plate line segment.

9. A plate line segmentation scheme as in claim 8 in which the plurality of plate line driver circuits are arranged into columns.

10. A plate line segmentation scheme as in claim 8 in which the plurality of plate line driver circuits are arranged into four columns coupled to four memory array sections, the first and second columns being located between a first and second memory array section, and the third and fourth columns being located between a third and fourth memory array section.

11. A plate line segmentation method comprising:

selecting a word line coupled to a row ferroelectric memory cells;

driving a first plate line segment coupled to a first portion of the row of ferroelectric memory cells; and

grounding a second plate line segment coupled to a second portion of the row of ferroelectric memory cells.

12. The method of claim 11 further comprising sensing a charge on bit lines corresponding to the first portion of the row of ferroelectric memory cells.

13. The method of claim 11 further comprising grounding bit lines corresponding to the second portion of the row of ferroelectric memory cells.

14. The method of claim 11 further comprising disabling a pre-charge circuit coupled to the first portion of the row of ferroelectric memory cells.

15. The method of claim 11 further comprising enabling a pre-charge circuit coupled to the second portion of the row of ferroelectric memory cells.

16. An architecture for a 1T/1C ferroelectric memory having segmented plate line comprising:

eight memory array sections having N rows and M columns of 1T/1C ferroelectric memory cells, N and M being multiples of two, each memory array section being divided into four sub-sections of memory cells;

a plurality of word lines associated with each memory array section; and

a plurality of plate line associated with each memory array section being divided into plate line segments coupled to each sub-section of memory cells,

such that only a single plate line segment is driven when a corresponding word line is driven.

17. The architecture of claim 16 further comprising a bank of sense amplifiers associated with each memory sub-section, only one bank being enabled corresponding to the plate line segment being driven.

18. The architecture of claim 16 further comprising a bank of pre-charge circuits associated with each memory sub-section, only one bank being disabled corresponding to the plate line segment being driven.

19. The architecture of claim 16 further comprising a column of plate line driver circuits coupled to each memory sub-section.

20. The architecture of claim 16 in which N is equal to 512 and M is equal to 64.