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Synchronous memory test system

  • US 5,995,424 A
  • Filed: 07/16/1997
  • Issued: 11/30/1999
  • Est. Priority Date: 07/16/1997
  • Status: Expired due to Term
First Claim
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1. A portable synchronous memory test system for identifying the type, control line configuration, width, depth, and access time of any one synchronous memory of a plurality of different synchronous memories, which comprises:

  • computer control means for executing program instructions, and supplying first timing control signals to said portable synchronous memory test system;

    memory test controller means in electrical communication with said computer control means for generating and issuing control signals to said any one synchronous memory;

    program delay line means in electrical communication with said computer control means and said memory test controller means for generating data latch strobes to implement a delay in finite steps between issuance of a read command by said memory test controller means to said any one synchronous memory and a reading of test patterns from said any one synchronous memory to determine an access time of said any one synchronous memory;

    data latch means in electrical communication with said computer control means, said memory test controller means, and said program delay line means and receiving said data latch strobes, for accommodating data writes into and reads from said any one synchronous memory;

    power supply means in electrical communication with said any one synchronous memory, said computer control means, said memory test controller means, said program delay line means, and said data latch means, for turning power to said any one synchronous memory on and off, and for providing a voltage bouncing input to said any one synchronous memory; and

    memory means in electrical communication with said computer control means, said memory test controller means, said program delay line means, said data latch means, and said power supply means, and having stored therein test patterns of control line configurations, and program instructions for executing a nested loop process to write said test patterns into said any one synchronous memory to evoke responses identifying part type, width, depth, and control line configuration of said any one synchronous memory.

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