Synchronous memory test system

• US 5,995,424 A
• Filed: 07/16/1997
• Issued: 11/30/1999
• Est. Priority Date: 07/16/1997
• Status: Expired due to Term

• Current Assignee: Neosem, Inc., Tanisys Technology, Inc. (Spirox Corporation)
• Original Assignee: Tanisys Technology, Inc. (Spirox Corporation)
• Inventors: Lawrence, Archer R, Little, Jack C
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Hoang, Huan
• Application Number:
  US08/895,307
• Time in Patent Office: 867 Days
• Field of Search: 365/201, 365/194, 365/233, 365/226, 365/189.05, 365/203, 371/21.1, 371/21.4
• US Class Current: 365/201
• CPC Class Codes: G01R 31/31908 Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
• CPC Class Codes: G01R 31/31914 Portable Testers
• CPC Class Codes: G01R 31/31915 In-circuit Testers
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 2029/5002 Characteristic
• CPC Class Codes: G11C 2029/5004 Voltage
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/10 Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Abstract

An automated, portable, and time conservative memory test system for identifying test parameters including type, control line configuration, depth, width, access time, and burst features of any one of a wide variety of synchronous memories including SDRAMs and SGRAMs, and whether an IC chip, bank, board or module, without requiring hardware modifications or additions to the memory device being identified, and without requiring storage of test patterns or characterizing, data in the memory device.

Claims

1. A portable synchronous memory test system for identifying the type, control line configuration, width, depth, and access time of any one synchronous memory of a plurality of different synchronous memories, which comprises:

computer control means for executing program instructions, and supplying first timing control signals to said portable synchronous memory test system;

memory test controller means in electrical communication with said computer control means for generating and issuing control signals to said any one synchronous memory;

program delay line means in electrical communication with said computer control means and said memory test controller means for generating data latch strobes to implement a delay in finite steps between issuance of a read command by said memory test controller means to said any one synchronous memory and a reading of test patterns from said any one synchronous memory to determine an access time of said any one synchronous memory;

data latch means in electrical communication with said computer control means, said memory test controller means, and said program delay line means and receiving said data latch strobes, for accommodating data writes into and reads from said any one synchronous memory;

power supply means in electrical communication with said any one synchronous memory, said computer control means, said memory test controller means, said program delay line means, and said data latch means, for turning power to said any one synchronous memory on and off, and for providing a voltage bouncing input to said any one synchronous memory; and

memory means in electrical communication with said computer control means, said memory test controller means, said program delay line means, said data latch means, and said power supply means, and having stored therein test patterns of control line configurations, and program instructions for executing a nested loop process to write said test patterns into said any one synchronous memory to evoke responses identifying part type, width, depth, and control line configuration of said any one synchronous memory.

2. The portable synchronous memory test system of claim 1, wherein virtual addresses of a size up to 256M words are converted to synchronous memory physical addresses ranging from 12 to 14 row address lines and from 8 to 14 column address lines.

3. The portable synchronous memory test system of claim 1, wherein said computer control means issues finite step control signals to said program delay line means, and a read command and a memory clock signal to said memory test controller means, and said memory test controller means in response thereto issues a delay start signal to said program delay line means and a data strobe to said data latch means upon elapse of a programmable delay controlled by said program delay line means to provide data read from said any one synchronous memory to said computer control means, said memory test controller means further providing a read signal sequence and a synchronization clock signal to said any one synchronous memory to synchronize reception of said read signal sequence by said any one synchronous memory and generation of said read signal sequence by said memory test controller means.

4. The portable synchronous memory test system of claim 1, wherein said plurality of synchronous memories includes SDRAMs and SGRAMs.

5. The portable synchronous memory test system of claim 1, wherein said memory test controller means includes a precharge bit register for activating a precharge bit of said any one synchronous memory in executing a precharge cycle preceding a read or write cycle of a row in a memory array.

6. The portable synchronous memory test system of claim 1, wherein said memory test controller means includes a WPB &

SP register for asserting a DSF signal during SGRAM identification to program internal SGRAM mode set, mask and color registers.