Semiconductor IC device having a memory and a logic circuit implemented with a single chip

• US 5,995,439 A
• Filed: 11/10/1998
• Issued: 11/30/1999
• Est. Priority Date: 03/08/1996
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd., Hitachi ULSI Engineering Corp
• Inventors: Yanagisawa, Kazumasa, Ayukawa, Kazushige, Tanaka, Hitoshi, Watanabe, Takao, Fujita, Ryo
• Primary Examiner(s): Phan, Trong
• Assistant Examiner(s): NGUYEN, HIEN N
• Application Number:
  US09/188,367
• Time in Patent Office: 385 Days
• Field of Search: 365/189.08, 365/51, 365/52, 365/63, 365/230.03, 365/233, 365/230.06, 365/195
• US Class Current: 365/230.03
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1042 using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module. In the bank module are arranged row-system circuits which operate independently of each other and a multiplicity of I/O lines which extend in a bit line direction.

Claims

1. A semiconductor integrated circuit device, comprising:

a plurality of first modules,

wherein each of said plurality of first modules includes;

a memory array having a plurality of word lines, a plurality of bit lines, and a plurality of memory cells arranged at the points of intersection thereof;

a plurality of global data lines extending in a first direction and coupled to the plurality of bit lines via a plurality of column switches;

a control circuit having a row decoder coupled to the plurality of word lines, and a column decoder coupled to the control nodes of the plurality of column switches; and

a plurality of address signal lines extending in the first direction and coupled to the control circuit via predetermined wires,

wherein said plurality of first modules are arranged in a row in the first direction, each of the plurality of global data lines is connected among said plurality of first modules, and each of the plurality of address signal lines is connected among said plurality of first modules.

2. A semiconductor integrated circuit device according to claim 1,

wherein each of said plurality of first modules further includes a first node for receiving a row-related bank selection signal and a second node for receiving a column-related bank selection signal.

3. A semiconductor integrated circuit device according to claim 2,

wherein each of said plurality of first modules further includes a clock signal line extending in the first direction and coupled to the control circuit via a predetermined wire,

wherein the clock signal line is connected among said plurality of first modules.

4. A semiconductor integrated circuit device according to claim 3, further comprising:

a main control circuit coupled to the plurality of address signal lines, the clock signal line, and the first and second nodes of said plurality of first modules,

wherein said main control circuit can supplies a first signal for selecting a second module which is one of said plurality of first modules to the first node of the second module and a second signal for selecting a third module which is another one of said plurality of first modules to the second node of the third module in a predetermined cycle of a clock.

5. A semiconductor integrated circuit device according to claim 4,

wherein said main control circuit supplies row address signals to the second modules via a part of the plurality of address signal lines and column address signals to the third module via the rest of the plurality of address signal lines when the first signal is supplied to the second module and the second signal is supplied to the third module.

6. A semiconductor integrated circuit device according to claim 5,

wherein said main control circuit outputs the row address signals, the column address signals, the first signal, and the second signal at a timing of a transition edge of a clock.

7. A semiconductor integrated circuit device according to claim 2, wherein said of the plurality of memory cells of said plurality of first modules is a DRAM type memory cell having one transistor and one capacitor.

8. A semiconductor integrated circuit device according to claim 5, wherein each of the plurality of memory cells of said plurality of first modules is a DRAM type memory cell having one transistor and one capacitor.

9. A semiconductor integrated circuit device according to claim 2,

wherein each of the plurality of memory cells of one of said plurality of first modules is a SRAM cell, a program-fixed mask memory cell, or a memory cell using a ferroelectric film, and

wherein each of the plurality of memory cells of another one of said plurality of first modules is a DRAM type memory cell having one transistor and one capacitor.

10. A semiconductor integrated circuit device according to claim 5,

wherein each of the plurality of memory cells of one of said plurality of first modules is a SRAM cell, a program-fixed mask memory cell, or a memory cell using a ferroelectric film, and

wherein each of the plurality of memory cells of another one of said plurality of first modules is a DRAM type memory cell having one transistor and one capacitor.

11. A semiconductor integrated circuit device according to claim 1, further comprising:

a second module including a plurality of main amplifiers,

wherein said second module adjoins one of the plurality of first modules which is placed at one end of the row of said plurality of first modules,

wherein the plurality of main amplifiers connected to the plurality of global data lines.

12. A semiconductor integrated circuit device according to claim 11, further comprising:

third module including a plurality of voltage generating circuits,

wherein said third module adjoins one of the plurality of first modules,

wherein each of said plurality of first modules further includes a plurality of power supply lines extending in the first direction, and

wherein each of the plurality of power supply lines is connected among said plurality of first modules, and is coupled to corresponding one of the plurality of voltage generating circuits of said third module.

13. A semiconductor integrated circuit device according to claim 12,

wherein the column decoder and the control nodes of the column switches are coupled via a plurality of column selection signal lines,

wherein the plurality of word lines and the plurality of column selection signal lines extend in a second direction which crosses the first direction substantially at a right angle,

wherein the plurality of bit lines extend in the first direction.

14. A semiconductor integrated circuit device according to claim 13, wherein each of the plurality of memory cells is a DRAM type memory cell having one transistor and one capacitor.