Synchronous memory device

• US 5,995,443 A
• Filed: 03/04/1999
• Issued: 11/30/1999
• Est. Priority Date: 04/18/1990
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): Nguyen, Tan T.
• Application Number:
  US09/262,114
• Time in Patent Office: 271 Days
• Field of Search: 365/233, 365/189.02, 365/230.03, 365/230.02
• US Class Current: 365/233.1
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 : Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 : Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 : Output synchronization
• CPC Class Codes: G11C 7/1069 : I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: G11C 8/00 : Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.

The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.

Claims

1. A synchronous memory device having a memory cell array divided into a plurality of subarrays, wherein each subarray includes a plurality of subarray sections, the memory device comprising:

clock receiver circuitry to receive an external clock signal from an external bus;

clock generation circuitry, coupled to the clock receiver circuitry, to generate a first internal clock signal having a clock edge which is synchronized with the external clock signal and to generate a second internal clock signal having a clock edge which is synchronized with the external clock signal;

a first subarray section having a first internal I/O line to access data from a first memory cell location and a second internal I/O line to access data from a second memory cell location, wherein the first and second memory cell locations are in the first subarray section;

a second subarray section having a first internal I/O line to access data from a third memory cell location and a second internal I/O line to access data from a fourth memory cell location, wherein the third and fourth memory cell locations are in the second subarray section;

output driver circuitry, including a first output driver and a second output driver, to output data onto the external bus in response to a read request; and

multiplexer circuitry, coupled to the output driver circuitry, wherein;

the multiplexer circuitry couples the first internal I/O line of the first subarray section to an input of the first output driver and couples the first internal I/O line of the second subarray section to an input of the second output driver in response to the clock edge of the first internal clock signal; and

the multiplexer circuitry couples the second internal I/O line of the first subarray section to an input of the first output driver and couples the second internal I/O line of the second subarray section to an input of the second output driver in response to the clock edge of the second internal clock signal.

2. The memory device of claim 1 wherein the memory device further includes data input receiver circuitry, coupled to the external bus, to input data from the bus in response to a write request wherein the data input receiver circuitry includes:

a first data input receiver, coupled to the external bus, to latch data from the external bus in response to the clock edge of the first internal clock signal; and

a second data input receiver, coupled to the external bus, to latch data from the bus in response to the clock edge of the second internal clock signal.

3. The memory device of claim 1 wherein the first internal clock signal is generated by a delay locked loop.

4. The memory device of claim 1 wherein the first internal clock signal and the second internal clock signal are substantially complementary.

5. The memory device of claim 4 wherein the first subarray section and the second subarray section are included in the same subarray.

6. The memory device of claim 1 further including an internal register for storing a value indicative of a number of clock cycles of the external clock signal to transpire before data is driven onto the external bus in response to a read request.

7. The memory device of claim 6 wherein the value represents a fraction or a whole number of clock cycles of the external clock.

8. The memory device of claim 1 further including a first plurality of sense amplifiers and a second plurality of sense amplifiers, wherein:

data accessed from a first memory cell location is latched in a sense amplifier of the first plurality of sense amplifiers and data accessed from the second memory cell location is latched in a sense amplifier of the second plurality of sense amplifiers; and

data accessed from a third memory cell location is latched in a sense amplifier of the first plurality of sense amplifiers and data accessed from the fourth memory cell location is latched in a sense amplifier of the second plurality of sense amplifiers.

9. The memory device of claim 8 wherein the first plurality of sense amplifiers is located proximal to a first side of the first subarray section and the second plurality of sense amplifiers is located proximal to a second side of the first subarray section.

10. The memory device of claim 9 wherein the first plurality of sense amplifiers is located proximal to a first side of the second subarray section and the second plurality of sense amplifiers is located proximal to a second side of the second subarray section.

11. The memory device of claim 1 wherein the first subarray section is automatically precharged after executing the read request.

12. The memory device of claim 1 further including a plurality of sense amplifiers located proximal to the first subarray section, wherein the plurality of sense amplifiers latch data from the first memory cell location and the second memory cell location in response to the read request.

13. The memory device of claim 12 wherein the data latched in the plurality of sense amplifiers is maintained in the sense amplifiers for a subsequent read request.

14. The memory device of claim 12 wherein the data latched in the plurality of sense amplifiers is maintained in the sense amplifiers and output by the output driver circuitry in response to the subsequent read request.

15. The memory device of claim 12 wherein the data latched in the plurality of sense amplifiers is maintained in the sense amplifiers and modified in response to a write request.

16. The memory device of claim 1 wherein the external clock signal has a fixed frequency.

17. The memory device of claim 1 wherein the clock edge of the first internal clock signal is a rising edge and the clock edge of the second internal clock signal is a rising edge.

18. The memory device of claim 1 wherein the output driver circuitry outputs a predetermined amount of data defined by block size information and wherein the block size information is a binary code.

19. The memory device of claim 18 wherein the block size information and the read request are included in a request packet.

20. The memory device of claim 19 wherein the block size information and the read request are included in the same request packet.

21. A synchronous memory device having a memory cell array divided into a plurality of subarrays, including a first subarray and a second subarray wherein each subarray includes a plurality of subarray sections, the memory device comprises:

clock receiver circuitry to receive an external clock signal from an external bus;

clock generation circuitry, coupled to the clock receiver circuitry, to generate a first internal clock signal having a clock edge which is synchronized with the external clock signal and to generate a second internal clock signal having a clock edge which is synchronized with the external clock signal;

a first subarray section of a first subarray, the first subarray section having a first internal I/O line to access data from a first memory cell location and a second internal I/O line to access data from a second memory cell location, wherein the first and second memory cell locations are in the first subarray section;

a second subarray section of a second subarray, the second subarray section having a first internal I/O line to access data from a third memory cell location and a second internal I/O line to access data from a fourth memory cell location, wherein the third and fourth memory cell locations are in the second subarray section;

output driver circuitry, including a first output driver and a second output driver, to output data onto the external bus in response to a read request; and

multiplexer circuitry, coupled to the output driver circuitry, wherein;

the multiplexer circuitry couples the first internal I/O line of the first subarray section to an input of the first output driver and couples the first internal I/O line of the second subarray section to an input of the second output driver in response to the clock edge of the first internal clock signal; and

the multiplexer circuitry couples the second internal I/O line of the first subarray section to an input of the first output driver and couples the second internal I/O line of the second subarray section to an input of the second output driver in response to the clock edge of the second internal clock signal.

22. The memory device of claim 21 wherein the first internal clock signal is generated by a delay locked loop.

23. The memory device of claim 21 wherein the first internal clock signal is generated by a first delay locked loop and the second internal clock signal is generated by a second delay locked loop.

24. The memory device of claim 21 further including a first plurality of sense amplifiers and a second plurality of sense amplifiers, wherein data accessed from a first memory cell location is latched in a sense amplifier of the first plurality of sense amplifiers and data accessed from the second memory cell location is latched in a sense amplifier of the second plurality of sense amplifiers.

25. The memory device of claim 24 wherein the first plurality of sense amplifiers is located proximal to a first side of the first subarray section and the second plurality of sense amplifiers is located proximal to a second side of the first subarray section.

26. The memory device of claim 24 further including a third plurality of sense amplifiers and a fourth plurality of sense amplifiers, wherein data accessed from a third memory cell location is latched in a sense amplifier of the third plurality of sense amplifiers and data accessed from the fourth memory cell location is latched in a sense amplifier of the fourth plurality of sense amplifiers.

27. The memory device of claim 26 wherein the third plurality of sense amplifiers is located proximal to a first side of the second subarray section and the fourth plurality of sense amplifiers is located proximal to a second side of the second subarray section.

28. The memory device of claim 21 further including a plurality of sense amplifiers located proximal to the first subarray section, wherein the plurality of sense amplifiers latch data from the first memory cell location and the second memory cell location in response to the read request.

29. A memory system having a synchronous memory device coupled to a bus, the memory device having a memory cell array divided into a plurality of subarrays, wherein each subarray includes a plurality of subarray sections, the memory system comprises:

clock receiver circuitry to receive a bus clock from the bus;

clock generation circuitry to generate a first clock edge which is synchronized with the bus clock and to generate a second clock edge which is synchronized with the bus clock;

a first subarray section having a first data line to access data from a first memory cell location and a second data line to access data from a second memory cell location, wherein the first and second memory cell locations are in the first subarray section;

a second subarray section having a first data line to access data from a third memory cell location and a second data line to access data from a fourth memory cell location, wherein the third and fourth memory cell locations are in the second subarray section;

output drivers, including a first output driver and a second output driver, to output a predetermined amount of data onto the bus in response to a read request; and

multiplexer circuitry, coupled to the output drivers, wherein;

the multiplexer circuitry couples the first data line of the first subarray section to an input of the first output driver and couples the first data line of the second subarray section to an input of the second output driver in response to the first clock edge; and

the multiplexer circuitry couples the second data line of the first subarray section to an input of the first output driver and couples the second data line of the second subarray section to an input of the second output driver in response to the second clock edge.

30. The memory system of claim 29 wherein clock generation circuitry includes a delay locked loop.

31. The memory system of claim 29 further including a register for storing bus clock information indicative of a number of clock cycles of the bus clock to transpire before data is driven onto the bus in response to a read request wherein the bus clock information represents a fraction or a whole number of clock cycles of the bus clock.

32. The memory system of claim 29 wherein the bus is external to the memory device.

33. The memory system of claim 29 wherein the bus further includes a plurality of conductors terminated by an impedance to a power source.

34. The memory system of claim 29 wherein the bus further includes a plurality of low voltage swing conductors.

35. The memory system of claim 34 wherein the low voltage swing is more than 0.25 volts and less than V_DD.

36. The memory system of claim 29 wherein the first subarray section and the second subarray section are included in the same subarray.

37. The memory system of claim 29 wherein the first subarray section is included in a first subarray and the second subarray section is included in a second subarray.