FM multiplex broadcasting receiver

• US 5,995,519 A
• Filed: 02/14/1997
• Issued: 11/30/1999
• Est. Priority Date: 04/12/1996
• Status: Expired due to Term

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Miwa, Kenji
• Primary Examiner(s): Pham, Chi H.
• Assistant Examiner(s): YAO, KWANG BIN
• Application Number:
  US08/799,371
• Time in Patent Office: 1,019 Days
• Field of Search: 370/503, 370/506, 370/509, 370/510, 370/512, 370/513, 370/514, 370/516, 370/520, 375/354, 375/357, 375/362, 375/365, 375/366, 375/368, 375/371, 371/48, 371/49.1, 371/67.1, 714/799, 714/800, 714/801, 714/804, 714/819
• US Class Current: 370/509
• CPC Class Codes: H04H 40/18 Arrangements characterised by circuits or components specially adapted for receiving
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence

Abstract

A receiver for FM Multiplex broadcast packet communications is provided that includes a block identifying code (BIC) detection circuit which determines whether a received packet is a data packet type or a parity packet type based on predetermined BIC patterns. The receiver further includes block counter circuitry that counts blocks in a synchronized frame and determines whether a received packet is a data type or a parity type (D/P) based on the count value. An abnormality detection circuit detects discrepancies between these two D/P determinations and indicates a synchronization abnormality. In another embodiment, the BIC detection circuit provides an indication of a received BIC type (BIC1-BIC4) based on predetermined BIC patterns while the block counter circuitry determines the BIC type based on the counted number of the block in a synchronized frame. In this case, the abnormality detection circuit detects discrepancies between the two BIC type determinations and indicates a synchronization abnormality. A history of detected abnormalities is stored in an abnormal history memory circuit. If the number of abnormalities detected exceeds a predetermined threshold within a predetermined period, a packet offset determining circuit then generates a signal for canceling the frame-in-synchronism state and initiates a resynchronization process.

Claims

1. A receiver for receiving digital data multiplexed on FM multiplex broadcast signals wherein a packet of digital information is structured as either a data packet comprising a block of binary data bits or as a parity packet comprising a block of binary parity bits and a frame comprises a plurality of packets, and wherein block synchronism of de-multiplexed data is determined at least in part by detecting a block synchronization code attached to the head of each packet and frame synchronism is determined at least in part by detecting a change in the block synchronization code occurring at predetermined blocks, said receiver comprising:

block counter circuitry, said block counter circuitry composing a counter for counting packets in a synchronized frame of received data and producing a first signal indicative of whether a received packet is of a data packet type or a parity packet type based on predetermined block count values;

a block identification code detection circuits said detection circuit comprising digital logic circuitry for detecting a block synchronization code in a received packet and producing a second signal indicative of whether a received packet is of a data type or a parity type based on predetermined synchronization code patterns; and

an abnormality determining circuit, said determining circuit comprising digital logic circuitry for comparing said second signal indicative of packet type determined from said synchronization code with said first signal indicative of packet type determined by said counter circuitry and outputting an abnormality indication signal when said first and second signals indicate different packet types.

2. A receiver for FM multiplex broadcasting according to claim 1, further comprising:

an abnormality history circuit comprising digital data storage circuitry for storing a bit pattern of accumulated abnormality indication signals produced by said abnormality determining circuit over a prescribed period; and

a packet offset determining circuit comprising logic circuitry for comparing a stored history of abnormality indication signals with a predetermined bit offset pattern indicative of a packet offset condition and providing a signal for canceling a frame-in-synchronism state and initiating frame resynchronization when a result of said comparing indicates a predetermined number of matching pattern bits.

3. A receiver for FM multiplex broadcasting according to claim 1, further comprising:

an abnormality history circuit comprising digital data storage circuitry for storing a bit pattern of accumulated abnormality indication signals produced by said abnormality determining circuit over a prescribed period; and

a packet offset determining circuit comprising logic circuitry for comparing a stored history of abnormality indication signals with a predetermined bit offset pattern indicative of a packet offset condition and providing a signal for canceling a frame-in-synchronism state and initiating frame resynchronization when a result of said comparing indicates a predetermined number of frequency or abnormality indication signals has been exceeded.

4. A receiver for receiving digital data multiplexed on FM multiplex broadcast signals wherein a packet of digital information is structured as either a data packet comprising a block of binary data bits or as a parity packet comprising a block of binary parity bits and a frame comprises a plurality of packets, and wherein block synchronism of de-multiplexed data is determined at least in part by detecting a block synchronization code attached to the head of each packet and frame synchronism is determined at least in part by detecting a change in the block synchronization code occurring at predetermined blocks, said receiver comprising:

block counter circuitry, said block counter circuitry comprising a counter for counting packets in a synchronized frame of received data and producing a first signal indicative of a block synchronization code type based on predetermined block count values;

a block identification code detection circuit, said detection circuit comprising digital logic circuitry for detecting a block synchronization code in a received packet and producing a second signal indicative of a synchronization code type based on predetermined synchronization code patterns; and

an abnormality determining circuit, said determining circuit comprising digital logic circuitry for comparing said second signal indicative of a synchronization code type determined from said synchronization code with said first signal indicative of a synchronization code type determined by said counter circuitry and outputting an abnormality indication signal when said first and second signals indicate different synchronization code types.

5. A receiver for FM multiplex broadcasting according to claim 4, further comprising;

an abnormality history circuit comprising digital data storage circuitry for storing a bit pattern of accumulated abnormality indication signals produced by said abnormality determining circuit over a prescribed period; and

a packet offset determining circuit comprising logic circuitry for comparing a stored history of abnormality indication signals with a predetermined bit offset pattern indicative of a packet offset condition and providing a signal for canceling a frame-in-synchronism state and initiating frame resynchronization when a result of said comparing indicates a predetermined number of matching pattern bits.

6. A receiver for FM multiplex broadcasting according to claim 4, further comprising:

an abnormality history circuit comprising digital data storage circuitry for storing a bit pattern of accumulated abnormality indication signals produced by said abnormality determining circuit over a prescribed period; and

a packet offset determining circuit comprising logic circuitry for comparing a stored history of abnormality indication signals with a predetermined bit offset pattern indicative of a packet offset condition and providing a signal for canceling a frame-in-synchronism state and initiating frame resynchronization when a result of said comprising indicates that a predetermined number or frequency of abnormality indication signals has been exceeded.

7. In an FM Multiplex broadcasting packet communications arrangement wherein a frame of transmitted digital information comprises a predetermined number of blocks which are either of a data packet type or a parity packet type and each block includes a header comprising a block identifying code (BIC) which may be used for block and frame synchronization purposes, and wherein certain change points indicated by changes in BICs within a frame are used to provide a means for radio receiver equipment to determine frame synchronization, and wherein different types of BICs also distinguish parity packets from data packets, and further wherein parity type packets occur only at specific prescribed blocks within a frame, identifiable by the sequential position of a block within a synchronized frame and/or by the type of BIC, a method for determining a packet offset condition indicative of an out-of-synchronization frame in a radio receiver, comprising the steps of:

a) counting blocks received in a synchronized frame;

b) determining from said counting whether a received block is a data packet or a parity packet;

c) detecting a BIC in a received block of data;

d) determining whether the BIC indicates that the received block is a data packet or a parity packet; and

e) generating a signal indicative of a packet abnormality whenever determinations of packet type made in steps (b) and (d) indicate different packet types.

8. A method as set forth in claim 7 further comprising the steps of:

storing packet abnormality indication signals over a predetermined period of time;

comparing a pattern of abnormality indication signals stored over a predetermined period of time with a prescribed bit pattern indicative of a frame-out-of-synchronism state; and

generating a signal for canceling a frame-in-synchronism state and initiating frame resynchronization when a result of said comparing indicates that a predetermined number or frequency of abnormality indication signals has been exceeded.