Apparatus and method for calibration of sleep mode clock in wireless communications mobile station

• US 5,995,820 A
• Filed: 06/17/1997
• Issued: 11/30/1999
• Est. Priority Date: 06/17/1997
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Gardner, William R., Young, Linley M., White, Peter P.
• Primary Examiner(s): Eisenzopf, Reinhard J.
• Assistant Examiner(s): Orgad, Edan
• Application Number:
  US08/877,217
• Time in Patent Office: 896 Days
• Field of Search: 455/343, 455/38.3, 455/574, 455/260, 455/334, 455/424, 455/38.1, 370/311, 370/314, 340/825.44
• US Class Current: 455/343.1
• CPC Class Codes: H04W 52/029 reducing the clock frequency of the controller
• CPC Class Codes: H04W 52/0293 having a sub-controller with a low clock frequency switching on and off a main controller with a high clock frequency
• CPC Class Codes: H04W 56/0035 detecting errors in frequency or phase
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

The present invention presents a calibrator for a mobile station of a TDMA wireless communications system such that the calibrator calibrates a low-frequency clock to a high frequency clock locked to system timing. When the mobile station is in idle mode (i.e., listening to a paging channel periodically, but otherwise taking no action), the control processor commands the mobile station to enter into sleep mode to minimize power consumption. During sleep mode, the high-frequency reference clock and all clocks derived from it are turned off. Only the calibrated low-frequency clock remains operating to clock the sleep logic.

Claims

1. A wireless communications mobile station comprising:

a. radio frequency circuitry for receiving and modulating radio signals;

b. first mixed signal circuitry operationally connected to the radio frequency circuitry for converting the modulated radio signals to digitized signals;

c. baseband processing circuitry operationally connected to said first mixed signal circuitry for processing said digitized signals;

d. second mixed signal circuitry operationally connected to the baseband processing circuitry for converting processed digitized signals to analog signals;

e. a speaker operationally connected to said second mixed signal circuitry for communicating speech derived from analog signals input into the speaker from said second mixed signal circuitry;

f. a first reference clock operationally connected to said baseband processing circuitry which provides a reference signal having a frequency;

g. a second clock which runs at a frequency lower than the frequency of said first reference clock, said second clock providing a reference signal during the operation of sleep mode;

h. a calibrator for calibrating said second clock before entry into sleep mode, said calibrator comprising;

(1) a sleep counter for counting cycles of said second clock during a specified number of system frames; and

(2) a calculator for calculating the duration of sleep mode in second clock cycles based upon the number reached by said sleep counter and the desired duration of sleep mode as a function of system frames;

i. a system frame counter, wherein the length of the time period during which the sleep counter counts the cycles of the second clock is controlled by the system frame counter; and

j. a calibration length register to which the TDMA frame counter is operationally connected, wherein the number of system frames to be counted by the TDMA frame counter during said time period is input into said calibration length register.

2. The wireless communications mobile station according to claim 1 wherein the baseband processing circuitry comprises a control processor and said control processor inputs the number of systems frames to be counted by the TDMA counter during said time period into the calibration length register.

3. A wireless communications mobile station comprising:

a. radio frequency circuitry for receiving and modulating radio signals;

b. first mixed signal circuitry operationally connected to the radio frequency circuitry for converting the modulated radio signals to digitized signals;

c. baseband processing circuitry operationally connected to said first mixed signal circuitry for processing said digitized signals;

d. second mixed signal circuitry operationally connected to the baseband processing circuitry for converting processed digitized signals to analog signals;

e. a speaker operationally connected to said second mixed signal circuitry for communicating speech derived from analog signals input into the speaker from said second mixed signal circuitry;

f. a first reference clock operationally connected to said baseband processing circuitry which provides a reference signal having a frequency;

g. a second clock which runs at a frequency lower than the frequency of said first reference clock said second clock providing a reference signal during the operation of sleep mode;

h. a calibrator for calibrating said second clock before entry into sleep mode, said calibrator comprising;

(1) a sleep counter for counting cycles of said second clock during a specified number of system frames; and

(2) a calculator for calculating the duration of sleep mode in second clock cycles based upon the number reached by said sleep counter and the desired duration of sleep mode as a function of systems frames;

i. a system frame counter, wherein the length of the time period during which the sleep counter counts the cycles of the second clock is controlled by the system frame counter; and

j. a calibration register, wherein at the end of the time period during which the sleep counter counts the cycles of the second clock, said frame counter causes the calibration register to latch onto the value in said sleep register.

4. The wireless communications mobile station according to claim 3 wherein said sleep register is operationally connected to said calibration register via a multiplexer.

5. The wireless communications mobile station according to claim 4 wherein said baseband processing circuitry comprises a control processor and said control processor is operationally connected to said multiplexer such that it can input a value into said calibration register.

6. A wireless communications mobile station comprising:

a. a mouthpiece for receiving sound waves and converting said sound waves into first analog signals;

b. first mixed signal circuitry operationally connected to the mouthpiece for converting said first analog signals to digitized signals;

c. baseband processing circuitry operationally connected to said first mixed signal circuitry for processing said digitized signals;

d. second mixed signal circuitry operationally connected to the baseband processing circuitry for converting processed digitized signals to second analog signals;

e. radio frequency circuitry for modulating said second analog signals and transmitting the modulated second analog signals;

f. a first reference clock operationally connected to said baseband processing circuitry which provides a reference signal having a frequency;

g. a second clock which runs at a frequency lower than the frequency of said first reference clock, said second clock providing a reference signal during the operation of sleep mode;

h. a calibrator for calibrating said second clock before entry into sleep mode, said calibrator comprising;

(1) a sleep counter for counting cycles of said second clock during a specified number of systems frames; and

(2) a calculator for calculating the duration of sleep mode in second clock cycles based upon the number reached by said sleep counter and the desired duration of sleep mode as a function of systems frames;

i. a system frame counter for controlling the length of the time period during which the sleep counter counts the cycles of the second clock; and

j. a calibration length register to which the system frame counter is operationally connected, wherein the number of system frames to be counted by the system frame counter during the time period during which the sleep counter counts the cycles of the second clock is input into said calibration length register.

7. The wireless communications mobile station according to claim 6 wherein the baseband processing circuitry comprises a control processor and said control processor inputs a value into the calibration length register.

8. The wireless communications mobile station according to claim 7 wherein, at the end of the time period during which the sleep counter counts the cycles of the second clock, said frame counter causes a calibration register to latch onto the value in said sleep register.

9. The wireless communications mobile station according to claim 8 wherein said sleep register is operationally connected to said calibration register via a multiplexer.

10. The wireless communications mobile station according to claim 9 wherein said baseband processing circuitry comprises a control processor and said control processor is operationally connected to said multiplexer such that it can input a value into said calibration register.

11. A calibrator for calibrating a sleep mode reference clock in a wireless communications mobile station comprising:

a. a sleep counter for counting cycles of said clock during a specified number of systems frames;

b. a calculator for calculating the duration of sleep mode in cycles of said clock based upon the number reached by said sleep counter and the desired duration of sleep mode as a function of systems frames;

c. a system frame counter for controlling the length of the time period during which the sleep counter counts the cycles of the clock; and

d. a calibration length register to which the system frame counter is operationally connected, wherein the number of system frames to be counted by the system frame counter during the time period during which the sleep counter counts the cycles of the second clock is input into said calibration length register.

12. The calibrator according to claim 11 wherein the mobile station a control processor and said control processor inputs a value into the calibration length register.

13. The calibrator according to claim 11 wherein, at the end of the time period during which the sleep counter counts the cycles of the clock, said system frame counter causes a calibration register to latch onto the value in said sleep register.

14. The calibrator according to claim 13 wherein said sleep register is operationally connected to said calibration register via a multiplexer.

15. The calibrator according to claim 14 wherein said mobile station comprises a control processor said control processor is operationally connected to said multiplexer such that it can input a value into said calibration register.

16. A wireless communications system comprising:

a. a mobile station,

b. a base station subsystem which controls the radio link with the mobile station, and

c. a network subsystem which is interfaced with a public fixed network and the base station subsystem, wherein said mobile station comprises the following;

(1) radio frequency circuitry for receiving and modulating radio signals;

(2) first mixed signal circuitry operationally connected to the radio frequency circuitry for converting the modulated radio signals to digitized signals;

(3) baseband processing circuitry operationally connected to said first mixed signal circuitry for processing said digitized signals;

(4) second mixed signal circuitry operationally connected to the baseband processing circuitry for converting processed digitized signals to analog signals;

(5) a speaker operationally connected to said second mixed signal circuitry for communicating speech derived from analog signals input into the speaker from said second mixed signal circuitry;

(6) a first reference clock operationally connected to said baseband processing circuitry which provides a reference signal having a frequency;

(7) a second clock which runs at a frequency lower than the frequency of said first reference clock, said second clock providing a reference signal during the operation of sleep mode;

(8) a calibrator for calibrating said second clock to said first reference clock before entry into sleep mode, said calibrator comprising;

(a) a sleep counter for counting cycles of said second clock during a specified number of systems frames; and

(b) a calculator for calculating the duration of sleep mode in second clock cycles based upon the number reached by said sleep counter and the desired duration of sleep mode as a function of systems frames;

(9) a system frame counter for controlling the length of the time period during which the sleep counter counts the cycles of the second clock; and

(10) a calibration length register to which the TDMA frame counter is operationally connected, wherein the number of systems frames to be counted by the TDMA frame counter during said time period is input into said calibration length register.

17. The wireless communications mobile station according to claim 16 wherein the baseband processing circuitry comprises a control processor and said control processor inputs the number of systems frames to be counted by the TDMA counter during said time period into the calibration length register.

18. A wireless communications system comprising:

a. a mobile station,

b. a base station subsystem which controls the radio link with the mobile station, and

c. a network subsystem which is interfaced with a public fixed network and the base station subsystem, wherein said mobile station comprises the following;

(1) radio frequency circuitry for receiving and modulating radio signals;

(2) first mixed signal circuitry operationally connected to the radio frequency circuitry for converting the modulated radio signals to digitized signals;

(3) baseband processing circuitry operationally connected to said first mixed signal circuitry for processing said digitized signals;

(4) second mixed signal circuitry operationally connected to the baseband processing circuitry for converting processed digitized signals to analog signals;

(5) a speaker operationally connected to said second mixed signal circuitry for communicating speech derived from analog signals input into the speaker from said second mixed signal circuitry;

(6) a first reference clock operationally connected to said baseband processing circuitry which provides a reference signal having a frequency;

(7) a second clock which runs at a frequency lower than the frequency of said first reference clock, said second clock providing a reference signal during the operation of sleep mode;

(8) a calibrator for calibrating said second clock to said first reference clock before entry into sleep mode, said calibrator comprising;

(a) a sleep counter for counting cycles of said second clock during a specified number of systems frames; and

(b) a calculator for calculating the duration of sleep mode in second clock cycles based upon the number reached by said sleep counter and the desired duration of sleep mode as a function of systems frames.

(9) a system frame counter for controlling the length of the time period during which the sleep counter counts the cycles of the second clock; and

(10) a calibration register for latching onto the value in said sleep register when induced by said frame counter at the end of the time period during which the sleep counter counts the cycles of the second clock.

19. The wireless communications mobile station according to claim 18 wherein said sleep register is operationally connected to said calibration register via a multiplexer.

20. The wireless communications mobile station according to claim 19 wherein said baseband processing circuitry comprises a control processor and said control processor is operationally connected to said multiplexer such that it can input a value into said calibration register.