Data processing system and method of permutation with replication within a vector register file

• US 5,996,057 A
• Filed: 04/17/1998
• Issued: 11/30/1999
• Est. Priority Date: 04/17/1998
• Status: Expired due to Term

• Current Assignee: Apple Computer Incorporated (Apple Inc.), International Business Machines Corporation, Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Apple Inc., International Business Machines Corporation, Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Olsson, Brett, Dubey, Pradeep Kumar, Hochsprung, Ronald Ray, Scales, Hunter Ledbetter III, Diefendorff, Keith Everett
• Primary Examiner(s): Pan, Daniel H.
• Application Number:
  US09/062,100
• Time in Patent Office: 592 Days
• Field of Search: 395/800.04, 395/800.05, 395/800.01, 395/800.23, 395/705, 395/800.08, 364/DIG. 1, 364/DIG. 2, 711/118, 711/3, 711/130, 711/157, 712/21, 712/9, 712/1, 712/24, 712/11, 712/213, 712/3.4, 712/5, 712/22, 380/25, 713/323, 713/324
• US Class Current: 712/5
• CPC Class Codes: G06F 15/8084 Special arrangements thereof, e.g. mask or switch
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/3816 Instruction alignment, e.g. cache line crossing

Abstract

The data processing system of the present invention loads three input operands, including two input vectors and a control vector, into vector registers and performs a permutation of the two input vectors as specified by the control vector, and further stores the result of the operation as the output operand in an output register. The control vector consists of sixteen indices, each uniquely identifying a single byte of input data in either of the input registers, and can be specified in the operational code or be the result of a computation previously performed within the vector registers. The specification of the control vector allows a vector-matrix operation to be performed on the input vectors by rearranging or replicating the input operand bytes in the bytes of the output register as a function of the control vector. This system provides a highly efficient register loading mechanism for data vectors misaligned in memory, and allows the computation of a serially dependent chain of binary functions within the vector registers.

Claims

1. A method for combining, in accordance with a control vector, at least a first input vector and a second input vector to create an output vector, each vector comprising at least first and second vector elements, the method comprising the steps of:

storing said first input vector;

storing said second input vector;

storing said control vector;

in response to the first vector element of said control vector, storing, as the first vector element of said output vector, a selected one of (1) the first vector element of the first input vector, (2) the second vector element of the first input vector, (3) the first vector element of the second input vector, or (4) the second vector element of the second input vector; and

in response to the second vector element of said control vector, storing, as the second vector element of said output vector, a selected one of (1) the first vector element of the first input vector, (2) the second vector element of the first input vector, (3) the first vector element of the second input vector, or (4) the second vector element of the second input vector.

2. The method of claim 1 wherein the vector elements of said input vectors comprise a set of 2ⁿ input vector elements, and wherein each of said vector elements of said control vector selects one of said 2ⁿ input vector elements.

3. The method of claim 1 wherein each of said first and second input vectors comprise 2^n-1 input vector elements, and wherein each of said vector elements of said control vector selects one of said 2ⁿ input vector elements.

4. A method for combining in an output vector, vector elements of a first input vector and a second input vector, selected in accordance with a control vector, each vector comprising at least first and second vector elements, the method comprising the steps of:

storing said first input vector;

storing said second input vector;

storing said control vector;

selecting, in response to each vector element of said stored control vector, a respective one of the vector elements of said stored input vectors; and

storing each of said selected vector elements as a respective one of the vector elements of said output vector, the output vector being the same size as the first input vector and the second input vector.

5. The method of claim 4 wherein the vector elements of said input vectors comprise a set of 2ⁿ input vector elements, and wherein each of said vector elements of said control vector selects one of said 2ⁿ input vector elements.

6. The method of claim 4 wherein each of said first and second input vectors comprise 2^n-1 input vector elements, and wherein each of said vector elements of said control vector selects one of said 2ⁿ input vector elements.

7. An apparatus for combining, in accordance with a control vector, at least a first input vector and a second input vector to create an output vector, each vector comprising at least first and second vector elements, the apparatus comprising:

a first vector register for storing said first input vector;

a second vector register for storing said second input vector;

a third vector register for storing said control vector;

a combination network coupled to the first vector register, to the second vector register and to the third vector register for selecting, in response to each vector element stored in said third vector, a respective one of vector elements stored in said first and said second vector registers; and

a fourth vector register for storing each of said selected vector elements.

8. The apparatus of claim 7 wherein the vector elements of said first and second vector registers comprise a set of 2ⁿ input vector elements, and wherein, in response to each of said vector elements of said control vector, the combination network selects one of said 2ⁿ input vector elements.

9. The apparatus of claim 7 wherein the vector elements of each of said first and second vector registers comprise 2^n-1 input vector elements, and wherein, in response to each of said vector elements of said control vector, the combination network selects one of said 2ⁿ input vector elements.