System and method for handling software interrupts with argument passing

• US 5,996,058 A
• Filed: 08/19/1996
• Issued: 11/30/1999
• Est. Priority Date: 08/19/1996
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Song, Seungyeon Peter, Nguyen, Le, Mohamed, Moataz A., Park, Heon-Chul
• Primary Examiner(s): An, Meng-Ai T.
• Assistant Examiner(s): Monestime, Mackly
• Application Number:
  US08/699,295
• Time in Patent Office: 1,198 Days
• Field of Search: 395/800.43, 395/800.01, 395/800.31, 395/739, 712/1, 712/31, 712/32, 712/34, 712/43, 710/265, 710/266, 710/264
• US Class Current: 712/31
• CPC Class Codes: G06F 15/17 using an input/output type connection, e.g. channel, I/O port
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked

Abstract

A multiprocessor architectural definition provides that a program executing on a first processor interrupts a second processor by executing a software interrupt instruction. The software interrupt instruction includes an argument field for passing information from a program requesting the software interrupt. The argument, along with the opcode, is saved in a register designated for holding the argument. The information communicated via the argument is used in one embodiment to indicate a cause of the interrupt. In an embodiment, the information communicated via the argument designates an interrupt service routine to be activated in the interrupted processor.

Claims

1. A computer system comprising:

a plurality of processors including a first processor and a second processor, the first processor and the second processor being mutually asymmetric with dissimilar control-handling and data-handling characteristics;

the first processor including a control logic for executing a software interrupt instruction that evokes a software interrupt in the second processor then defers interrupt and exception handling operations to the second processor;

the software interrupt instruction having an argument field for passing information from the first processor to the second processor;

the second processor including a control logic responsive to the software interrupt for accessing the information of the argument field.

2. A computer system according to claim 1 wherein the software interrupt instruction argument field includes a field for transferring information identifying a condition within the first processor for evoking an interrupt in the second processor.

3. A computer system according to claim 1 wherein the software interrupt instruction argument field includes a field for transferring information identifying an instruction code within a storage in the second processor at which a software interrupt servicing routine is located, the software interrupt servicing routine being activated by the software interrupt.

4. A computer system according to claim 1 wherein the software interrupt instruction is a JOIN instruction causing a software interrupt in the second processor and activating a software interrupt servicing routine identified by an offset argument in the argument field.

5. A computer system according to claim 4 wherein the JOIN instruction argument field includes a field for transferring information identifying a condition within the first processor for evoking an interrupt in the second processor.

6. A computer system according to claim 4 wherein the JOIN instruction argument field holds an offset argument indicative of a branch address for branching to a software interrupt servicing routine.

7. A computer system according to claim 1 wherein:

the second processor is a control processor having a defined data path width; and

the first processor is a vector processor having a wide data path width that is substantially larger than the data path width of the second processor.

8. A computer system according to claim 1 wherein:

the first processor control logic for executing a software interrupt instruction evoking a software interrupt in the second processor further includes control logic deactivating the first processor to an idle state.

9. A computer system according to claim 1 wherein an interrupt and exception subhandler operating on a second processor responds to an interrupt or exception on the first processor for handling the interrupt and exception conditions of the first processor in a first execution thread and the second processor in a second execution thread, the first and second execution threads being controlled in combination by the second processor.

10. A computer system according to claim 1 further comprising:

a coprocessor coupled between the first processor and the second processor, the coprocessor including a register for holding the argument field.

11. A first processor in a multiple processor computer system comprising:

a control logic for executing a software interrupt instruction that evokes a software interrupt in a second processor of the multiple processors then defers interrupt ind exception handling operations to the second processor;

the software interrupt instruction having an argument field for passing information from the first processor to the second processor, the argument field including a field for transferring information identifying a condition within the first processor for evoking an interrupt in the second processor.

12. A first processor in a multiple processor computer system comprising:

a control logic for executing a software interrupt instruction that evokes a software interrupt in a second processor of the multiple processors then defers interrupt and exception handling operations to the second processor;

the software interrupt instruction having an argument field for passing information from the first processor to the second processor, the argument field including a field for transferring information identifying an instruction code within a storage in the second processor at which a software interrupt servicing routine is located, the software interrupt servicing routine being activated by the software interrupt.

13. A first processor in a multiple processor computer system comprising:

a control logic for executing a software interrupt instruction that evokes a software interrupt in a second processor of the multiple processors then defers interrupt and exception handling operations to the second processor;

the software interrupt instruction having an argument field for passing information from the first processor to the second processor, wherein the software interrupt instruction is a JOIN instruction causing a software interrupt in the second processor and activating a software interrupt servicing routine identified by an offset argument in the argument field.

14. A first processor according to claim 13 wherein the JOIN instruction argument field includes a field for transferring information identifying a condition within the first processor for evoking an interrupt in the second processor.

15. A first processor according to claim 13 wherein the JOIN instruction argument field holds an offset argument indicative of a branch address for branching to a software interrupt servicing routine.

16. A first processor in a multiple processor computer system comprising:

a control logic for executing a software interrupt instruction that evokes a software interrupt in a second processor of the multiple processors then defers interrupt and exception handling operations to the second processor;

the software interrupt instruction having an argument field for passing information from the first processor to the second processor, wherein;

the second processor is a control processor having a defined data path width; and

the first processor is a vector processor having a wide data path width that is substantially larger than the data path width of the second processor.

17. A first processor in a multiple processor computer system comprising:

a control logic for executing a software interrupt instruction that evokes a software interrupt in a second processor of the multiple processors then defers interrupt and exception handling operations to the second processor;

the software interrupt instruction having an argument field for passing information from the first processor to the second processor, wherein;

the first processor control logic is capable of executing a software interrupt instruction evoking a software interrupt in the second processor and further includes control logic deactivating the first processor to an idle state.

18. A first processor in a multiple processor computer system comprising:

a control logic for executing a software interrupt instruction that evokes a software interrupt in a second processor of the multiple processors then defers interrupt and exception handling operations to the second processor;

the software interrupt instruction having an argument field for passing information from the first processor to the second processor, wherein an interrupt and exception subhandler operating on a second processor responds to an interrupt or exception on the first processor for handling the interrupt and exception conditions of the first processor in a first execution thread and the second processor in a second execution thread, the first and second execution threads being controlled in combination by the second processor.

19. A method of operating a computer system comprising:

operating a plurality of processors including a first processor and a second processor, the first processor and the second processor being mutually

asymmetric with dissimilar control-handling and data-handling characteristics;

executing a software interrupt instruction on the first processor that evokes a software interrupt in the second processor;

deferring to the second processor control of interrupt and exception handling operations controlling the first processor;

passing information from the first processor to the second processor via the software interrupt instruction having an argument field; and

accessing the information of the argument field in the second processor in response to the software interrupt.

20. A method according to claim 19 further comprising:

transferring information identifying a condition within the first processor for evoking an interrupt in the second processor via a field in the software interrupt instruction argument field.

21. A method according to claim 19 further comprising:

transferring information identifying an instruction code within a storage in the second processor at which a software interrupt servicing routine is located via a field in the software interrupt instruction argument field; and

activating the software interrupt servicing routine by the software interrupt.