Partitioned multiply and add/subtract instruction for CPU with integrated graphics functions

• US 5,996,066 A
• Filed: 10/10/1996
• Issued: 11/30/1999
• Est. Priority Date: 10/10/1996
• Status: Expired due to Term

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Yung, Robert
• Primary Examiner(s): Kim, Kenneth S.
• Application Number:
  US08/722,442
• Time in Patent Office: 1,146 Days
• Field of Search: 364/736.02, 364/748.07, 395/562, 708/501, 708/523, 712/5, 712/9, 712/22, 712/221
• US Class Current: 712/221
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

An optimized, superscalar microprocessor architecture for supporting graphics operations in addition to the standard microprocessor integer and floating point operations. A number of specialized graphics instructions and accompanying hardware for executing them are disclosed to optimize the execution of graphics instruction with minimal additional hardware for a general purpose CPU.

Claims

1. A microprocessor for performing both graphics and non-graphics operations, comprising:

a first source register for storing a first plurality of partitioned values;

a second source register for storing a second plurality of partitioned values;

a destination register;

multiplier logic having first and second inputs coupled to two of said registers and being configured to perform a partitioned multiply on a plurality of said values in each of said two registers at the same time in response to a multiply/add Opcode; and

an adder having a first input coupled to a third one of said registers and a second input coupled to an output of said multiplier logic, and being configured to perform a partitioned addition of a plurality of values in said third register with a plurality of values output from said multiplier in response to said multiply/add Opcode.

2. The microprocessor of claim 1 further comprising a mask register configured to mask designated partitioned fields of at least one of said registers.

3. The microprocessor of claim 1 further comprising rounding logic for rounding a result of said multiply and add operations, but not an intermediate result.

4. A microprocessor for performing both graphics and non-graphics operations, comprising:

a first source register for storing a first plurality of partitioned values;

a second source register for storing a second plurality of partitioned values;

a destination register;

multiplier logic having first and second inputs coupled to two of said registers and being configured to perform a partitioned multiply on a plurality of said values in each of said two registers at the same time in response to a multiply/subtract Opcode; and

a subtractor having a first input coupled to a third one of said registers and a second input coupled to an output of said multiplier logic, and being configured to perform a partitioned subtraction between a plurality of values in said third register and a plurality of values output from said multiplier in response to said multiply/subtract Opcode.

5. The microprocessor of claim 4 further comprising a mask register configured to mask designated partitioned fields of at least one of said registers.

6. The microprocessor of claim 4 further comprising rounding logic for rounding a result of said multiply and subtract operations, but not an intermediate result.

7. A computer readable memory storing computer executable program code accessible by a microprocessor for performing both graphics and non-graphics operations, comprising:

a computer usable medium having computer readable code embodied therein including an OPcode instruction configured to cause said microprocessor to perform a partitioned multiply of a plurality of first register values packed into a first register by a plurality of second register values packed into a second register at the same time to provide a plurality of multiply results, and a partitioned subtract between said multiply results and a plurality of third register values packed into a third register.

8. The memory of claim 7 further comprising an OPcode instruction for setting a mask configured to mask designated partitioned fields of at least one of said registers.

9. A computer readable memory storing computer executable program code accessible by a microprocessor for performing both graphics and non-graphics operations, comprising:

a computer usable medium having computer readable code embodied therein including an OPcode instruction configured to cause said microprocessor to perform a partitioned multiply of a plurality of first register values packed into a first register by a plurality of second register values packed into a second register at the same time to provide a plurality of multiply results, and a partitioned add of said multiply results to a plurality of third register values packed into a third register.

10. The memory of claim 9 further comprising an OPcode instruction for setting a mask configured to mask designated partitioned fields of at least one of said registers.