Partitioned multiply and add/subtract instruction for CPU with integrated graphics functions
First Claim
Patent Images
1. A microprocessor for performing both graphics and non-graphics operations, comprising:
- a first source register for storing a first plurality of partitioned values;
a second source register for storing a second plurality of partitioned values;
a destination register;
multiplier logic having first and second inputs coupled to two of said registers and being configured to perform a partitioned multiply on a plurality of said values in each of said two registers at the same time in response to a multiply/add Opcode; and
an adder having a first input coupled to a third one of said registers and a second input coupled to an output of said multiplier logic, and being configured to perform a partitioned addition of a plurality of values in said third register with a plurality of values output from said multiplier in response to said multiply/add Opcode.
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Abstract
An optimized, superscalar microprocessor architecture for supporting graphics operations in addition to the standard microprocessor integer and floating point operations. A number of specialized graphics instructions and accompanying hardware for executing them are disclosed to optimize the execution of graphics instruction with minimal additional hardware for a general purpose CPU.
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Citations
10 Claims
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1. A microprocessor for performing both graphics and non-graphics operations, comprising:
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a first source register for storing a first plurality of partitioned values; a second source register for storing a second plurality of partitioned values; a destination register; multiplier logic having first and second inputs coupled to two of said registers and being configured to perform a partitioned multiply on a plurality of said values in each of said two registers at the same time in response to a multiply/add Opcode; and an adder having a first input coupled to a third one of said registers and a second input coupled to an output of said multiplier logic, and being configured to perform a partitioned addition of a plurality of values in said third register with a plurality of values output from said multiplier in response to said multiply/add Opcode. - View Dependent Claims (2, 3)
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4. A microprocessor for performing both graphics and non-graphics operations, comprising:
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a first source register for storing a first plurality of partitioned values; a second source register for storing a second plurality of partitioned values; a destination register; multiplier logic having first and second inputs coupled to two of said registers and being configured to perform a partitioned multiply on a plurality of said values in each of said two registers at the same time in response to a multiply/subtract Opcode; and a subtractor having a first input coupled to a third one of said registers and a second input coupled to an output of said multiplier logic, and being configured to perform a partitioned subtraction between a plurality of values in said third register and a plurality of values output from said multiplier in response to said multiply/subtract Opcode. - View Dependent Claims (5, 6)
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7. A computer readable memory storing computer executable program code accessible by a microprocessor for performing both graphics and non-graphics operations, comprising:
a computer usable medium having computer readable code embodied therein including an OPcode instruction configured to cause said microprocessor to perform a partitioned multiply of a plurality of first register values packed into a first register by a plurality of second register values packed into a second register at the same time to provide a plurality of multiply results, and a partitioned subtract between said multiply results and a plurality of third register values packed into a third register. - View Dependent Claims (8)
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9. A computer readable memory storing computer executable program code accessible by a microprocessor for performing both graphics and non-graphics operations, comprising:
a computer usable medium having computer readable code embodied therein including an OPcode instruction configured to cause said microprocessor to perform a partitioned multiply of a plurality of first register values packed into a first register by a plurality of second register values packed into a second register at the same time to provide a plurality of multiply results, and a partitioned add of said multiply results to a plurality of third register values packed into a third register. - View Dependent Claims (10)
Specification