System and method for the injection and cancellation of a bias voltage in an attenuated circuit
First Claim
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1. An apparatus for eliminating a bias voltage injected into a circuit, the apparatus comprising:
- an attenuator, having an attenuator input and an attenuator output, the attenuator input is connected to an input signal;
a summing network having first and second inputs and an output, the first input is connected to the attenuator output, the second input is connected to a voltage source; and
an output node, electrically coupled to the output of the summing network;
wherein the voltage at the output node is the analog equivalent of the input signal.
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Abstract
A system and method for injecting and canceling a bias voltage in an attenuated circuit is presented. The attenuated circuit is disposed within a tri-state logic-level measurement apparatus. The bias voltage is provided to ensure that when the measurement apparatus is floating, it floats at the tri-state voltage. In one embodiment, a summing network is connected to an attenuator, a first voltage generator which provides a bias voltage and a second voltage generator which provides a cancellation voltage. In another embodiment, a FET amplifier is provided in place of the summing network.
5 Citations
9 Claims
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1. An apparatus for eliminating a bias voltage injected into a circuit, the apparatus comprising:
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an attenuator, having an attenuator input and an attenuator output, the attenuator input is connected to an input signal; a summing network having first and second inputs and an output, the first input is connected to the attenuator output, the second input is connected to a voltage source; and an output node, electrically coupled to the output of the summing network; wherein the voltage at the output node is the analog equivalent of the input signal. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An apparatus for eliminating a bias voltage injected into a circuit, the apparatus comprising:
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an attenuator, having an input and an output, the input of the attenuator is connected to an input signal; A FET amplifier having an FET input and FET output, the FET input is connected to the attenuator output; and an output node, electrically coupled to the FET output; wherein the voltage at the output node is the analog equivalent of the input signal. - View Dependent Claims (8, 9)
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Specification