Assembly and method for testing integrated circuit devices

• US 5,996,102 A
• Filed: 08/26/1997
• Issued: 11/30/1999
• Est. Priority Date: 02/06/1996
• Status: Expired due to Term

• Current Assignee: Telefonaktiebolaget LM Ericsson
• Original Assignee: Telefonaktiebolaget LM Ericsson
• Inventors: Haulin, Tord L.
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Iqbal, Nadeem
• Application Number:
  US08/920,077
• Time in Patent Office: 826 Days
• Field of Search: 371/21.4, 371/22.31, 371/22.32, 371/25.1, 371/27.5, 371/27.3, 371/57.2, 395/183.15, 364/481, 364/482, 364/483, 364/489, 364/551.01, 364/718, 324/765, 324/538, 324/756, 714/8, 714/25, 714/32, 714/47, 714/721, 714/726, 714/727, 714/734, 714/740
• US Class Current: 714/740
• CPC Class Codes: G01R 31/31903 tester configuration
• CPC Class Codes: G11C 29/24 Accessing extra cells, e.g. dummy cells or redundant cells

Abstract

A testing assembly, and an associated method, for testing an integrated circuit device. The testing assembly is capable of testing an integrated circuit device having a large number of input and output terminals formed of either single-ended terminals or differential terminals. Static testing, both functional and parametric, can be performed upon the integrated circuit device. Additionally, dynamic testing of the integrated circuit device, even integrated circuit devices operable at high frequencies, is possible through operation of the testing assembly. Test signals are applied by way of signal rails to the device undergoing testing. A test signal response indicator is coupled to observe responses to the test signals.

Claims

1. A testing assembly for testing an integrated circuit device having a plurality of terminals, said testing assembly comprising:

a voltage signal generator for generating test signals of selected voltage levels;

a first signal rail coupled to receive the test signals generated by said voltage signal generator and positionable to extend along at least a portion of the integrated circuit device, said first signal rail for conducting the test signals generated by said voltage signal generator therealong;

a first group of impedance elements positioned in series with said first signal rail, the impedance elements of said first group of impedance elements corresponding in number with a first subset of the terminals of the plurality of terminals of the integrated circuit device, each impedance element of said first group of impedance elements coupled between said first signal rail and a terminal of at least first selected terminals of a first group of the plurality of terminals, thereby to apply the test signals conducted along said first signal rail to the first selected terminals, each impedance element of said first group of impedance elements of an impedance level generally matching impedance levels of at least portions of the integrated circuit device;

testing means that is capable of testing at least one element of the integrated circuit device, said one element selected from the group consisting of a receiver, a transmitter, and a termination unit; and

a test signal-response indicator coupled to selected terminals of a second group of the plurality of terminals of the integrated circuit device, said test signal-response indicator for indicating values of output signals generated at the terminals responsive to application of the test signals to the terminals.

2. The testing assembly of claim 1 wherein the test signals generated by said voltage signal generator are formed by the plurality of signal portions, each signal portion of a selected voltage level.

3. The testing assembly of claim 1 further comprising:

a second signal rail coupled to receive the test signals generated by said voltage signal generator, said second signal rail also positionable to extend along the at least a portion of the integrated circuit device, said second signal rail for conducting the test signals generated by said voltage signal generator therealong; and

a second group of impedance elements positioned in series with said second signal rail, the impedance elements of said second group of impedance elements corresponding in number with the terminals of the plurality of terminals of the integrated circuit device, each impedance element of said second group of impedance elements coupled between said second signal rail and a terminal of at least second selected terminals of the first group of the plurality of terminals, thereby to apply the test signals conducted along said second signal rail to the second selected terminals, each impedance element of said second group of impedance elements of an impedance level generally matching impedance levels of portions of the integrated circuit device.

4. The testing assembly of claim 3 wherein said voltage signal generator comprises a first output port and a second output port, said first signal rail coupled to said first output port and said second signal rail coupled to said second output port.

5. The testing assembly of claim 4 wherein the plurality of terminals include differential terminal pairs, each terminal pair having a positive terminal and a negative terminal, and wherein said first group of impedance elements connect said first signal rail to the positive terminals of the differential terminal pairs and said second group of impedance elements connect said second signal rail to negative terminals of the differential terminal pairs.

6. The testing assembly of claim 5 wherein the test signals generated by said voltage signal generator comprise positive differential voltage signals applied to the differential terminal pairs.

7. The testing assembly of claim 5 wherein the test signals generated by said voltage signal generator comprise negative differential voltage signals applied to the differential terminal pairs.

8. The testing assembly of claim 5 wherein the test signals generated by said voltage signal generator comprise a plurality of different, differential voltage signals applied to the differential terminal pairs.

9. The testing assembly of claim 1 wherein the plurality of terminals includes single-ended terminals, and wherein said first signal rail is coupled to said single-ended terminals.

10. The testing assembly of claim 9 wherein the test signals generated by said voltage signal generator are of voltage levels at least as large as a selected, minimum voltage level.

11. The testing assembly of claim 9 wherein the test signals generated by said voltage signal generator are of voltage levels less than a selected voltage level.

12. The testing assembly of claim 1 wherein said test signal response indicator comprises a digital value indicator.

13. The testing assembly of claim 12 wherein the digital value indicator comprises a boundary scan device.

14. The testing assembly of claim 13 wherein said boundary scan device comprises a test data output of a boundary scan element forming a portion of the integrated circuit device.

15. The testing assembly of claim 1 further comprising a contact determiner for determining whether said first signal rail contacts properly with the at least first selected terminals of the first group of the terminals of the integrated circuit device.

16. The testing assembly of claim 1 wherein the test signals generated by said voltage signal generator are of characteristics which, when applied to the integrated circuit device, test for dynamic operatiblity of the integrated circuit device.

17. The testing assembly of claim 1 wherein the integrated circuit device further comprises a pulse-signal comparator-receiver, said voltage signal generator further for generating a first signal pulse and a second signal pulse for application to the comparator-receiver, the first and second signal pulses, respectively, offset in phase relative to one another, and the second signal pulse of a greater maximum value than a maximum value of the first signal pulse and of a greater minimum value than a minimum value of the first signal pulse, and the comparator-receiver of the integrated circuit device for generating a test pulse when the first signal pulse is of a value greater than a value of the second signal pulse.

18. The testing assembly of claim 16 wherein the first group of the plurality of terminals each comprise a transmitter portion and wherein the test pulse generated by the comparator-receiver is applied to transmitter portions of each of the plurality of terminals.

19. In a method for dynamic testing of an integrated circuit device having an internal circuit portion and a plurality of bidirectional terminals, each bidirectional terminal having a receiver, a transmitter, and a pulse-signal comparator-receiver, an improvement of a method for testing dynamic operation of the internal circuit portion by applying a test pulse having a first selected pulse width thereto utilizing a test signal generator, the test signal generator capable of generating a pulse having no smaller than a second pulse width, the second pulse width larger than the first pulse width, said method comprising the steps of:

generating a first signal pulse at the test signal generator, the first signal pulse having a first-signal minimum signal value and first-signal maximum signal value;

generating a second signal pulse at the test signal generator, the second signal pulse having a second-signal minimum signal, the second-signal minimum signal value greater than the first-signal minimum signal value, and a second signal-maximum signal value, the second-signal maximum signal value greater than the first-signal maximum signal value, the second signal pulse generated at a selected time delay relative to generation of the first signal pulse during said step of generating the first signal pulse, thereby to be offset in phase relative to the first signal pulse;

concurrently applying the first signal pulse and the second signal pulse to the pulse-signal comparator receiver of the integrated circuit device;

forming a test pulse at the pulse signal comparator-receiver of the integrated circuit device responsive to application of the first and second signal pulses, respectively, during said step of applying, the test pulse of a pulse width responsive to the phase by which the first and second signal pulses, respectively, are offset from one another;

providing the test pulse formed during said step of forming to the transmitters of the bidirectional terminals; and

observing operation of the integrated circuit device responsive to the test pulse provided during said step of providing.

20. In a testing assembly for testing a device under test, the device under test having a plurality of terminals, the testing assembly having a plurality of probe elements, each probe element for contacting with a separate terminal of the plurality of terminals, an improvement of a contact determiner for determining electrical contact of each of the probe elements with each of the at least selected terminals of the device under test, said contact determiner comprising:

a plurality of switch devices, a separate switch device of said plurality of switch devices associated with each separate probe element of the testing assembly, each switch device having a first side and a second side;

a voltage source coupled in series to the first side of each switch device of said plurality of switch devices;

a plurality of annunciators, a separate annunciator associated with each separate terminal of the at least selected terminals of the device under test and probe element of the testing assembly, each annunciator coupled to a second side of a switch device of said plurality of switch devices associated with a corresponding one of the at least selected terminals; and

each switch device of said plurality of switch devices positioned in a closed position when the probe element associated therewith fails to contact with a terminal of the plurality of terminals, thereby to power the annunciator to annunciate lack of the electrical contact between the probe element and the terminal.

21. A method for testing an integrated circuit device having a plurality of terminals, said method comprising the steps of:

connecting a testing assembly to at least a portion of said plurality of terminals of said integrated circuit device, said integrated circuit device having a plurality of elements that share access to either a single terminal or a single set of terminals;

disabling at least a first element of said integrated circuit device;

enabling at least a second element of said integrated circuit device;

testing said second element of said integrated circuit device;

reading an output response of said integrated circuit device; and

terminating the testing of said second element of said integrated circuit device.

22. The method according to claim 21, wherein:

the step of disabling further comprises the step of disabling at least a transmitter and a termination unit;

the step of enabling further comprises the step of enabling at least a receiver; and

the step of testing further comprises the step of testing said receiver.

23. The method according to claim 22, wherein:

the step of testing said receiver further comprises the step of testing differential receivers for sensitivity or common mode range.

24. The method according to claim 22, wherein:

the step of testing said receiver further comprises the step of testing said receiver for gain or offset, said receiver being single-ended.

25. The method according to claim 21, wherein:

the step of disabling further comprises the step of disabling at least a termination unit;

the step of enabling further comprises the step of enabling at least a receiver and a transmitter; and

the step of testing further comprises the step of testing said transmitter.

26. The method according to claim 25, wherein:

the step of testing said transmitter further comprises the step of testing differential transmitters for level or drive strength.

27. The method according to claim 25, wherein:

the step of testing said transmitter further comprises the step of testing said transmitter for level or drive strength, said transmitter being single-ended.

28. The method according to claim 21, wherein:

the step of disabling further comprises the step of disabling at least a transmitter;

the step of enabling further comprises the step of enabling at least a receiver and a termination unit; and

the step of testing further comprises the step of testing said termination unit.

29. The method according to claim 28, wherein:

the step of testing said termination unit further comprises the step of testing an impedance aspect of said termination unit.

30. The method according to claim 29, further comprising the steps of:

enabling at least said transmitter and retesting said termination unit after the step of testing said termination unit; and

wherein the step of retesting said termination unit further comprises the step of retesting an impedance aspect of said termination unit.