Assembly and method for testing integrated circuit devices
First Claim
1. A testing assembly for testing an integrated circuit device having a plurality of terminals, said testing assembly comprising:
- a voltage signal generator for generating test signals of selected voltage levels;
a first signal rail coupled to receive the test signals generated by said voltage signal generator and positionable to extend along at least a portion of the integrated circuit device, said first signal rail for conducting the test signals generated by said voltage signal generator therealong;
a first group of impedance elements positioned in series with said first signal rail, the impedance elements of said first group of impedance elements corresponding in number with a first subset of the terminals of the plurality of terminals of the integrated circuit device, each impedance element of said first group of impedance elements coupled between said first signal rail and a terminal of at least first selected terminals of a first group of the plurality of terminals, thereby to apply the test signals conducted along said first signal rail to the first selected terminals, each impedance element of said first group of impedance elements of an impedance level generally matching impedance levels of at least portions of the integrated circuit device;
testing means that is capable of testing at least one element of the integrated circuit device, said one element selected from the group consisting of a receiver, a transmitter, and a termination unit; and
a test signal-response indicator coupled to selected terminals of a second group of the plurality of terminals of the integrated circuit device, said test signal-response indicator for indicating values of output signals generated at the terminals responsive to application of the test signals to the terminals.
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Accused Products
Abstract
A testing assembly, and an associated method, for testing an integrated circuit device. The testing assembly is capable of testing an integrated circuit device having a large number of input and output terminals formed of either single-ended terminals or differential terminals. Static testing, both functional and parametric, can be performed upon the integrated circuit device. Additionally, dynamic testing of the integrated circuit device, even integrated circuit devices operable at high frequencies, is possible through operation of the testing assembly. Test signals are applied by way of signal rails to the device undergoing testing. A test signal response indicator is coupled to observe responses to the test signals.
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Citations
30 Claims
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1. A testing assembly for testing an integrated circuit device having a plurality of terminals, said testing assembly comprising:
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a voltage signal generator for generating test signals of selected voltage levels; a first signal rail coupled to receive the test signals generated by said voltage signal generator and positionable to extend along at least a portion of the integrated circuit device, said first signal rail for conducting the test signals generated by said voltage signal generator therealong; a first group of impedance elements positioned in series with said first signal rail, the impedance elements of said first group of impedance elements corresponding in number with a first subset of the terminals of the plurality of terminals of the integrated circuit device, each impedance element of said first group of impedance elements coupled between said first signal rail and a terminal of at least first selected terminals of a first group of the plurality of terminals, thereby to apply the test signals conducted along said first signal rail to the first selected terminals, each impedance element of said first group of impedance elements of an impedance level generally matching impedance levels of at least portions of the integrated circuit device; testing means that is capable of testing at least one element of the integrated circuit device, said one element selected from the group consisting of a receiver, a transmitter, and a termination unit; and a test signal-response indicator coupled to selected terminals of a second group of the plurality of terminals of the integrated circuit device, said test signal-response indicator for indicating values of output signals generated at the terminals responsive to application of the test signals to the terminals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. In a method for dynamic testing of an integrated circuit device having an internal circuit portion and a plurality of bidirectional terminals, each bidirectional terminal having a receiver, a transmitter, and a pulse-signal comparator-receiver, an improvement of a method for testing dynamic operation of the internal circuit portion by applying a test pulse having a first selected pulse width thereto utilizing a test signal generator, the test signal generator capable of generating a pulse having no smaller than a second pulse width, the second pulse width larger than the first pulse width, said method comprising the steps of:
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generating a first signal pulse at the test signal generator, the first signal pulse having a first-signal minimum signal value and first-signal maximum signal value; generating a second signal pulse at the test signal generator, the second signal pulse having a second-signal minimum signal, the second-signal minimum signal value greater than the first-signal minimum signal value, and a second signal-maximum signal value, the second-signal maximum signal value greater than the first-signal maximum signal value, the second signal pulse generated at a selected time delay relative to generation of the first signal pulse during said step of generating the first signal pulse, thereby to be offset in phase relative to the first signal pulse; concurrently applying the first signal pulse and the second signal pulse to the pulse-signal comparator receiver of the integrated circuit device; forming a test pulse at the pulse signal comparator-receiver of the integrated circuit device responsive to application of the first and second signal pulses, respectively, during said step of applying, the test pulse of a pulse width responsive to the phase by which the first and second signal pulses, respectively, are offset from one another; providing the test pulse formed during said step of forming to the transmitters of the bidirectional terminals; and observing operation of the integrated circuit device responsive to the test pulse provided during said step of providing.
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20. In a testing assembly for testing a device under test, the device under test having a plurality of terminals, the testing assembly having a plurality of probe elements, each probe element for contacting with a separate terminal of the plurality of terminals, an improvement of a contact determiner for determining electrical contact of each of the probe elements with each of the at least selected terminals of the device under test, said contact determiner comprising:
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a plurality of switch devices, a separate switch device of said plurality of switch devices associated with each separate probe element of the testing assembly, each switch device having a first side and a second side; a voltage source coupled in series to the first side of each switch device of said plurality of switch devices; a plurality of annunciators, a separate annunciator associated with each separate terminal of the at least selected terminals of the device under test and probe element of the testing assembly, each annunciator coupled to a second side of a switch device of said plurality of switch devices associated with a corresponding one of the at least selected terminals; and each switch device of said plurality of switch devices positioned in a closed position when the probe element associated therewith fails to contact with a terminal of the plurality of terminals, thereby to power the annunciator to annunciate lack of the electrical contact between the probe element and the terminal.
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21. A method for testing an integrated circuit device having a plurality of terminals, said method comprising the steps of:
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connecting a testing assembly to at least a portion of said plurality of terminals of said integrated circuit device, said integrated circuit device having a plurality of elements that share access to either a single terminal or a single set of terminals; disabling at least a first element of said integrated circuit device; enabling at least a second element of said integrated circuit device; testing said second element of said integrated circuit device; reading an output response of said integrated circuit device; and terminating the testing of said second element of said integrated circuit device. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30)
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Specification