Silicon etching process for making microchannel plates

• US 5,997,713 A
• Filed: 05/08/1998
• Issued: 12/07/1999
• Est. Priority Date: 05/08/1997
• Status: Expired due to Term

• Current Assignee: Nanosciences Corporation
• Original Assignee: Nanosciences Corporation
• Inventors: Steinbeck, John, Beetz, Charles P. Jr., Boerstler, Robert W., Winn, David R.
• Primary Examiner(s): Nuzzolillo, Maria
• Assistant Examiner(s): Martin, Angela J.
• Application Number:
  US09/074,712
• Time in Patent Office: 578 Days
• Field of Search: 205/124, 205/219, 205/221, 205/223, 205/656, 205/665, 205/674, 205/675
• US Class Current: 205/124
• CPC Class Codes: B81B 1/004 Through-holes, i.e. extending from one face to the other face of the wafer
• CPC Class Codes: B81C 1/00166 Electrodes
• CPC Class Codes: B81C 1/00595 Control etch selectivity
• CPC Class Codes: B81C 2201/0114 Electrochemical etching, anodic oxidation
• CPC Class Codes: C25F 3/12 of semiconducting materials
• CPC Class Codes: H01J 43/246 Microchannel plates [MCP] image amplification tubes using MCP H01J31/507
• CPC Class Codes: H01J 9/02 Manufacture of electrodes or electrode systems
• CPC Class Codes: H01L 21/3063 Electrolytic etching
• CPC Class Codes: Y10S 977/888 Shaping or removal of materials, e.g. etching

Abstract

An element with elongated, high aspect ratio channels such as microchannel plate is fabricated by electrochemical etching of a p-type silicon element in a electrolyte to form channels extending through the element. The electrolyte may be an aqueous electrolyte. For use as a microchannel plate, the; the silicon surfaces of the channels can be converted to insulating silicon dioxide, and a dynode material with a high electron emissivity can be deposited onto the insulating surfaces of the channels. New dynode materials are also disclosed.

Claims

1. A method of forming high aspect ratio channels at preselected locations in a silicon element comprising the steps of:

(a) providing a p-doped silicon element having front and rear surfaces;

(b) forming a plurality of pits in the front surface of the element at preselected locations on said surface; and

(c) maintaining the front surface of the element and a counterelectrode in contact with an electrolyte while maintaining the element at a positive potential with respect to the counterelectrode, so that the element is etched preferentially at said pits to form channels extending side-by-side through the silicon element, from said front surface towards said rear surface.

2. A method as claimed in claim 1 wherein said electrolyte is an aqueous electrolyte.

3. A method as claimed in claim 2 wherein said aqueous electrolyte includes fluoride ions and has a pH of about 1 to 7.

4. A method as claimed in claim 3 wherein said aqueous electrolyte has a fluoride concentration of about 0.25 to about 5 M.

5. A method as claimed in claim 3 wherein said aqueous electrolyte includes an acid other than HF and a fluoride salt.

6. A method as claimed in claim 5 wherein said fluoride salt is selected from the group consisting of fluoroborate salts.

7. A method as claimed in claim 5 wherein said fluoride salt is NH₄ F.

8. A method as claimed in claim 3 wherein said electrolyte includes HCl and NH₄ F.

9. A method as claimed in claim 3 wherein said aqueous electrolyte includes a surfactant.

10. A method as claimed in claim 1 wherein said electrolyte is a non-aqueous electrolyte.

11. A method as claimed in claim 10 wherein said non-aqueous electrolyte includes less than about 100 parts per million water by weight.

12. A method as claimed in claim 1 further comprising the step of forming openings to said channels at said rear surface of said element.

13. A method as claimed in claim 12 wherein said step of forming said openings includes the step of removing material from said rear surface after forming said channels.

14. A method as claimed in claim 12 further comprising the step of providing an electron-emissive dynode material on interior surfaces of said channels.

15. A method as claimed in claim 14 further comprising the step of forming an electrically insulating layer on the interior surfaces of said channels prior to said step of providing said dynode material.

16. A method as claimed in claim 15 wherein said step of forming an electrically insulating layer includes the step of oxidizing silicon in said element at said channel surfaces.

17. A method as claimed in claim 15 wherein said step of forming an electrically insulating layer includes the step of depositing electrically insulating material in said channels.

18. A method as claimed in claim 14 wherein said dynode material is selected from the group consisting of nitrogen and oxygen doped or undoped polysilicon;

SnO₂. Sb;

SnO₂ ;

indium tin oxide (ITO);

MgIn₂ O_4-x ;

InGaO_3-x ;

ZnSnO_3-x ;

Zn₂ In₂ O_5-x ;

ZnGa₂ O_4-x ;

Cr₂ O₃ ;

MnO_2-x and Mn₂ O_3-x ;

(where 0≦

x≦

1) potassium silicides;

calcium suicides;

barium silicides;

cesium suicides;

magnesium silicides;

manganese suicides; and

Pb_y O_x (where 1≦

x≦

3 and 1≦

y≦

2).

19. A method as claimed in claim 14 further comprising the step of depositing an electrically conductive material on at least one of the front and rear surfaces of said element by directing the conductive material onto said at least one surface at an oblique angle to such surface.

20. A method as claimed in claim 1 wherein said step of forming said pits includes the step of forming a layer of a silicon oxide or silicon nitride on said front surface, forming apertures in said layer at said preselected locations, and anisotropically etching the silicon in said element through said apertures.

21. A method as claimed in claim 1 wherein said pits taper from a relatively wide opening at said front surface to a relatively narrow point beneath said front surface.

22. A microchannel plate comprising an element having a front surface, a rear surface and a plurality of channels extending therethrough, said channels having interior surfaces, and a dynode material on said interior surfaces, said dynode material being selected from the group consisting of nitrogen and oxygen doped or undoped polysilicon;

SnO₂. Sb;

SnO₂ ;

indium tin oxide (ITO);

MgIn₂ O_4-x ;

InGaO_3-x ;

ZnSnO_3-x ;

Zn₂ In₂ O_5-x ;

ZnGa₂ O_4-x ;

Cr₂ O₃ ;

MnO_2-x and Mn₂ O_3-x (where 0≦

x≦

1);

potassium silicides;

calcium silicides;

barium silicides;

cesium silicides;

magnesium silicides;

manganese silicides; and

Pb_y O_x (where 1≦

x≦

3 and 1≦

y≦

2).

23. A microchannel plate as claimed in claim 22 wherein said element includes a silicon body and a layer of an insulating material on said interior surfaces of said channels between said dynode material and said silicon body.

24. A microchannel plate as claimed in claim 23 wherein said layer of insulating material includes silicon dioxide.

25. A microchannel plate as claimed in claim 22 further comprising electrically conductive electrodes overlying said front and rear surfaces in contact with said dynode layers but not occluding said channels.

26. A p-doped silicon body having a front surface, a rear surface and a plurality of channels extending therethrough at regularly spaced locations, at substantially constant center-to-center distances said channels having diameters between about 100 nm and 2 μ

m and aspect ratios above about 20;

1.