Method of testing semiconductor

• US 5,998,228 A
• Filed: 04/15/1997
• Issued: 12/07/1999
• Est. Priority Date: 11/16/1993
• Status: Expired due to Fees

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Mathieu, Gaetan L., Eldridge, Benjamin N., Grube, Gary W., Khandros, Igor Y.
• Primary Examiner(s): Booth, Richard A
• Assistant Examiner(s): MURPHY, JOHN E
• Application Number:
  US08/839,759
• Time in Patent Office: 966 Days
• Field of Search: 438/14, 438/15, 29/843, 428/601, 428/620, 439/91, 439/912, 324/754, 324/762, 228/179.1, 228/180.1, 228/180.21, 228/180.22, 257/690, 257/696, 257/688
• US Class Current: 438/15
• CPC Class Codes: B23K 1/0008 specially adapted for particular articles or work
• CPC Class Codes: B23K 20/004 Wire welding
• CPC Class Codes: B23K 2101/40 Semiconductor devices
• CPC Class Codes: C23C 18/1605 by masking
• CPC Class Codes: C23C 18/165 Multilayered product layered product B32B
• CPC Class Codes: C25D 21/02 Heating or cooling
• CPC Class Codes: C25D 5/22 Electroplating combined with mechanical treatment during the deposition
• CPC Class Codes: C25D 5/605 Surface topography of the layers, e.g. rough, dendritic or nodular layers
• CPC Class Codes: C25D 7/123 Semiconductors first coated with a seed layer or a conductive layer
• CPC Class Codes: G01R 1/07342 the body of the probe being at an angle other than perpendicular to test object, e.g. probe card
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: G01R 31/2863 Contacting devices, e.g. sockets, burn-in boards or mounting fixtures in general G01R1/04
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/4889 Connection or disconnection of other leads to or from wire-like parts, e.g. wires
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 2224/02311 : Additive methods
• CPC Class Codes: H01L 2224/03912 : the bump being used as a mask for patterning the bonding area
• CPC Class Codes: H01L 2224/0401 : Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 : Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/0558 : being stacked
• CPC Class Codes: H01L 2224/05599 : Material
• CPC Class Codes: H01L 2224/05624 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/11003 : for holding or transferring the bump preform
• CPC Class Codes: H01L 2224/1132 : Screen printing, i.e. using a stencil
• CPC Class Codes: H01L 2224/11334 : using preformed bumps
• CPC Class Codes: H01L 2224/1134 : Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/1147 : using a lift-off mask
• CPC Class Codes: H01L 2224/1184 : involving a mechanical process, e.g. planarising the bump connector
• CPC Class Codes: H01L 2224/13022 : the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 2224/13124 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13582 : Two-layer coating
• CPC Class Codes: H01L 2224/13639 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13644 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13647 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13655 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13657 : Cobalt [Co] as principal constituent
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/274 : by blanket deposition of the material of the layer connector
• CPC Class Codes: H01L 2224/29075 : Plural core members
• CPC Class Codes: H01L 2224/29099 : Material
• CPC Class Codes: H01L 2224/2929 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/293 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/45014 : Ribbon connectors, e.g. rectangular cross-section
• CPC Class Codes: H01L 2224/45015 : being circular
• CPC Class Codes: H01L 2224/45124 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/4556 : Disposition, e.g. coating on a part of the core
• CPC Class Codes: H01L 2224/45572 : Two-layer stack coating
• CPC Class Codes: H01L 2224/45599 : Material
• CPC Class Codes: H01L 2224/48624 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48644 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48724 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48744 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48824 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48844 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/49109 : outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73203 : Bump and layer connectors
• CPC Class Codes: H01L 2224/81801 : Soldering or alloying
• CPC Class Codes: H01L 2224/83851 : being an anisotropic conductive adhesive
• CPC Class Codes: H01L 2224/85201 : Compression bonding
• CPC Class Codes: H01L 2224/85205 : Ultrasonic bonding
• CPC Class Codes: H01L 2224/85399 : Material
• CPC Class Codes: H01L 2224/90 : Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06555 : Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06572 : Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/27 : Manufacturing methods
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/72 : Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/90 : Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01045 : Rhodium [Rh]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/20104 : Temperature range 100 C=<T<150 C, 373.15 K =< T < 423.15K
• CPC Class Codes: H01L 2924/20105 : Temperature range 150 C=<T<200 C, 423.15 K =< T < 473.15K
• CPC Class Codes: H01L 2924/206 : Length ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01R 12/52 : connecting to other rigid printed circuits or like structures
• CPC Class Codes: H05K 1/141 : One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters H05K1/142 and H05K1/147 take precedence
• CPC Class Codes: H05K 2201/0397 : Tab forming integral conductive tabs H05K3/4092
• CPC Class Codes: H05K 2201/068 : wherein the coefficient of thermal expansion is important
• CPC Class Codes: H05K 2201/1031 : Surface mounted metallic connector elements
• CPC Class Codes: H05K 2201/10318 : Surface mounted metallic pins
• CPC Class Codes: H05K 2201/10378 : Interposers
• CPC Class Codes: H05K 2201/10719 : Land grid array [LGA]
• CPC Class Codes: H05K 2201/10734 : Ball grid array [BGA]; Bump grid array
• CPC Class Codes: H05K 2201/10757 : Bent leads
• CPC Class Codes: H05K 2201/10878 : Means for retention of a lead in a hole
• CPC Class Codes: H05K 2201/10909 : Materials of terminal, e.g. of leads or electrodes of components
• CPC Class Codes: H05K 2201/10946 : Leads attached onto leadless component after manufacturing the component
• CPC Class Codes: H05K 3/20 : by affixing prefabricated conductor pattern H05K1/187, H05K3/046, H05K3/4658, H05K3/4682 takes precedence
• CPC Class Codes: H05K 3/308 : Adaptations of leads connectors to printed circuits H01R12/00
• CPC Class Codes: H05K 3/326 : the printed circuit having integral resilient or deformable parts, e.g. tabs or parts of flexible circuits H05K3/365 takes precedence
• CPC Class Codes: H05K 3/3421 : Leaded components
• CPC Class Codes: H05K 3/3426 : characterised by the leads
• CPC Class Codes: H05K 3/368 : parallel to each other H05K3/361 takes precedence
• CPC Class Codes: H05K 3/4015 : using auxiliary conductive elements, e.g. pieces of metal foil, metallic spheres
• CPC Class Codes: H05K 3/4092 : Integral conductive tabs, i.e. conductive parts partly detached from the substrate
• CPC Class Codes: H05K 7/1069 : with spring contact pieces
• CPC Class Codes: Y02P 70/50 : Manufacturing or production processes characterised by the final manufactured product
• CPC Class Codes: Y10S 977/712 : formed from plural layers of nanosized material, e.g. stacked structures
• CPC Class Codes: Y10S 977/723 : On an electrically insulating substrate
• CPC Class Codes: Y10T 29/49004 : including measuring or testing of device or component part
• CPC Class Codes: Y10T 29/49117 : Conductor or circuit manufacturing
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49144 : by metal fusion
• CPC Class Codes: Y10T 29/49147 : Assembling terminal to base
• CPC Class Codes: Y10T 29/49149 : by metal fusion bonding
• CPC Class Codes: Y10T 29/49169 : Assembling electrical component directly to terminal or elongated conductor
• CPC Class Codes: Y10T 29/49171 : with encapsulating
• CPC Class Codes: Y10T 29/49204 : Contact or terminal manufacturing
• CPC Class Codes: Y10T 29/49208 : by assembling plural parts
• CPC Class Codes: Y10T 29/4922 : with molding of insulation
• CPC Class Codes: Y10T 29/49812 : Temporary protective coating, impregnation, or cast layer
• CPC Class Codes: Y10T 428/12396 : Discontinuous surface component
• CPC Class Codes: Y10T 428/12528 : Semiconductor component

Abstract

Resilient contact structures are mounted directly to bond pads on semiconductor dies, prior to the dies being singulated (separated) from a semiconductor wafer. This enables the semiconductor dies to be exercised (e.g., tested and/or burned-in) by connecting to the semiconductor dies with a circuit board or the like having a plurality of terminals disposed on a surface thereof. Subsequently, the semiconductor dies may be singulated from the semiconductor wafer, whereupon the same resilient contact structures can be used to effect interconnections between the semiconductor dies and other electronic components (such as wiring substrates, semiconductor packages, etc.). Using the all-metallic composite interconnection elements of the present invention as the resilient contact structures, burn-in can be performed at temperatures of at least 150° C., and can be completed in less than 60 minutes.

Claims

1. Method of testing semiconductor devices, prior to their being singulated from a semiconductor wafer, comprising:

permanently mounting a plurality of resilient contact structures directly to a plurality of first terminals on a plurality of semiconductor devices which are resident on a semiconductor wafer, each of said resilient contact structures having a tip and extending from a surface of the semiconductor device to which it is mounted;

urging a substrate having a plurality of second terminals towards the surfaces of the semiconductor devices resident on the semiconductor wafer to effect a plurality of electrical connections between respective ones of the second terminals and tips of the resilient contact structures; and

providing signals to the second terminals of the substrate to exercise, including powering up and/or burning-in, at least a portion of the plurality of semiconductor devices resident on the semiconductor wafer.

2. Method, according to claim 1, wherein:

the resilient contact structures are composite interconnection elements.

3. Method, according to claim 1, wherein:

the resilient contact structures are mounted by plating to the first terminals of the semiconductor devices.

4. Method, according to claim 1, wherein:

the resilient contact structures are anchored by a continuous overcoat to the first terminals of the semiconductor devices.

10. Method, according to claim 1, further comprising:

after testing the plurality of semiconductor devices, singulating them from the semiconductor wafer.

11. Method, according to claim 10, further comprising:

after singulating the semiconductor devices from the semiconductor wafer, with the resilient contact structures, effecting electrical connections between selected one or more of the semiconductor devices and a wiring substrate.

12. Method, according to claim 11, wherein the electrical connections are effected by:

mechanically biasing the semiconductor device against the wiring substrate.

13. Method, according to claim 11, wherein the electrical connections are effected by:

soldering or brazing the tips of the resilient contact structures to corresponding third terminals on the wiring substrate.

14. Method, according to claim 1, further comprising:

joining contact tip structures to the tips of the resilient contact structures.

15. Method, according to claim 14, wherein:

the contact tip structures are pre-fabricated on a sacrificial substrate; and

further comprising removing the sacrificial substrate after joining the contact tip structures to the resilient contact elements.

16. Method, according to claim 15, wherein:

the contact tip structures comprise at least one layer of a conductive metallic material.

17. Method, according to claim 15, wherein:

the sacrificial substrate is a silicon wafer.

18. Method, according to claim 1, further comprising:

powering up at least a portion of the unsingulated semiconductor devices by making pressure connections to the resilient contact structures on the portion of the unsingulated semiconductor devices; and

heating the semiconductor devices to a temperature of at least 150°

C. for less than 60 minutes.

19. Method, according to claim 1, wherein:

the resilient contact structures are hermetically sealed to the terminals.

20. Method, according to claim 1, wherein the terminals are formed by:

depositing a masking layer over a blanket conductive layer; and

providing openings in the masking layer at the desired position of each first terminal; and

providing additional openings in the masking layer, said additional openings defining portions of the blanket conductive layer which will perform a function selected from the group consisting of interconnecting two or more terminals, providing ground and/or power planes, and providing one or more capacitors directly upon the semiconductor device.

5. Method of testing and mounting semiconductor devices, comprising:

prior to a plurality of semiconductor devices being singulated from a semiconductor wafer;

permanently mounting a plurality of resilient contact structures directly to a plurality of first terminals on a surface of at least one of the plurality of semiconductor devices, said resilient contact structures each having a tip and extending from the surface of the semiconductor device;

urging a substrate having a plurality of second terminals towards the surface of the semiconductor device to effect a plurality of pressure connections between respective second terminals and tips of the resilient contact structures; and

providing signals to the second terminals of the substrate to test the semiconductor semiconductor device;

after testing the semiconductor semiconductor device;

singulating the semiconductor device from the wafer; and

mounting the semiconductor device to an electronic component, connections being made between the resilient contact structures of the semiconductor device and third terminals of the electronic component.

6. Method, according to claim 5, wherein:

the resilient contact structures are composite interconnection elements.

7. Method, according to claim 5, wherein:

the electronic component is a wiring substrate.

8. Method, according to claim 5, further comprising:

prior to the plurality of semiconductor devices being singulated from a semiconductor wafer;

mounting a plurality of resilient contact structures directly to a plurality of first terminals on a surface of a plurality of semiconductor devices, said resilient contact structures each having a tip and extending from the surface of the semiconductor device;

urging a substrate having a plurality of second terminals towards the surface of the semiconductor device to effect a plurality of pressure connections between respective second terminals and tips of the resilient contact structures; and

providing signals to the second terminals of the substrate to test the plurality of semiconductor semiconductor devices;

after testing the semiconductor devices;

singulating the devices from the wafer; and

mounting the devices to electronic components, connections being made between the resilient contact structures of the semiconductor device and terminals of the electronic components.

9. Method, according to claim 8, further comprising:

mounting more than one of the semiconductor devices to a single one of the electronic components.