Process to fabricate the non-silicide region for electrostatic discharge protection circuit
First Claim
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1. A method to fabricate a non-silicided region for electrostatic discharge (ESD) protection circuit, said method comprising steps of:
- providing a substrate having field oxide regions to define a first region, a second region and a third region;
forming a silicon oxide layer on said substrate;
forming a polysilicon layer on said silicon oxide layer;
etching back said silicon oxide layer and said polysilicon layer to define a gate and a gate oxide on said second region and said third region, a protective layer composing said silicon oxide and said polysilicon layer on said first region;
performing a first ion implantation containing N-type conducting dopants on said first region and said second region to form a lightly doped drain (LDD) regions in said second region;
performing a second ion implantation containing P-type conducting dopants on said third region to form LDD regions;
defining a silicon oxide layer to form spacers for said polysilicon layer of said first region and said gates for said second region and said third region;
performing a third ion implantation containing N-type conducting dopants on said first region and said second region to form source/drain regions for said second region;
performing a fourth ion implantation containing P-type conducting dopants on said third region to form source/drain regions;
performing a self-aligned silicided process to form a silicide layer on said gate and said source/drain regions for said second region and said third region, and on said polysilicon of said first region;
etching back said protective layer to form a gate for an ESD protective device; and
performing a fifth ion implantation containing N-type conducting dopants on said first region to form source/drain regions of said ESD protective device.
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Abstract
The present invention discloses a method to fabricate the non-silicide region for an ESD protective devices in a substrate. Firstly, a substrate is provided and it has field oxide regions to define an electrostatic discharge (ESD) region, a PMOS region and an NMOS region. A gate and a gate oxide for the NMOS region and the PMOS region are define. An N-type and a P-type ion implantation are respectively performed to form a lightly doped drain (LDD) for said NMOS region and said PMOS region. A P-type and an N-type implantation is implemented to form source/drain regions for the NMOS device and the PMOS device, respectively. Afterwards, a silicon oxide layer is defined to form spacers for the polysilicon layer and the gates for the NMOS region and the PMOS region. A self-aligned silicide process is performed to form a silicide layer on the gate and the source/drain regions for the PMOS device and the NMOS device. The polysilicon layer is etched back to form a gate for a ESD protective device and an implantation process is performed to form source/drain regions of the ESD protective device.
58 Citations
20 Claims
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1. A method to fabricate a non-silicided region for electrostatic discharge (ESD) protection circuit, said method comprising steps of:
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providing a substrate having field oxide regions to define a first region, a second region and a third region; forming a silicon oxide layer on said substrate; forming a polysilicon layer on said silicon oxide layer; etching back said silicon oxide layer and said polysilicon layer to define a gate and a gate oxide on said second region and said third region, a protective layer composing said silicon oxide and said polysilicon layer on said first region; performing a first ion implantation containing N-type conducting dopants on said first region and said second region to form a lightly doped drain (LDD) regions in said second region; performing a second ion implantation containing P-type conducting dopants on said third region to form LDD regions; defining a silicon oxide layer to form spacers for said polysilicon layer of said first region and said gates for said second region and said third region; performing a third ion implantation containing N-type conducting dopants on said first region and said second region to form source/drain regions for said second region; performing a fourth ion implantation containing P-type conducting dopants on said third region to form source/drain regions; performing a self-aligned silicided process to form a silicide layer on said gate and said source/drain regions for said second region and said third region, and on said polysilicon of said first region; etching back said protective layer to form a gate for an ESD protective device; and performing a fifth ion implantation containing N-type conducting dopants on said first region to form source/drain regions of said ESD protective device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method to fabricate a non-silicided region for electrostatic discharge (ESD) protection circuit, said method comprising steps of:
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providing a substrate having field oxide regions to define a first region, a second region and a third region; forming a silicon oxide layer on said substrate; forming a polysilicon layer on said silicon oxide layer; etching back said silicon oxide layer and said polysilicon layer to define a gate and a gate oxide on said second region and said third region, and a protective layer composing said silicon oxide and said polysilicon layer on said first region; performing a first ion implantation containing N-type conducting dopants on said first region and said second region to form a lightly doped drain (LDD) region in said second region; performing a second ion implantation containing P-type conducting dopants on said third region to form a LDD region; defining a silicon oxide layer to form spacers for said polysilicon layer of said first region and said gates for said second region and said third region; performing a third ion implantation containing N-type conducting dopants on said first region and said second region to form source/drain regions for said second region; performing a fourth ion implantation containing P-type conducting dopants on said third region to form source/drain regions; forming a metal layer on all said regions; performing a first rapid thermal annealing (RTA) process to form a silicide layer on said gate and said source/drain regions for said second region and said third region, and on said protective layer of said first region; removing said unreacted metal during said first RTA process by using a wet etching; performing a second RTA process; etching back said protective layer to form a gate for an ESD protective device; and performing a fifth ion implantation containing N-type conducting dopants on said first region to form source/drain regions of said ESD protective device. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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Current AssigneeTaiwan Semiconductor Manufacturing Company Limited
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Original AssigneeTexas Instruments, Inc.
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InventorsWu, Shye-Lin
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Primary Examiner(s)CHAUDHARI, CHANDRA P
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Application NumberUS09/057,866Time in Patent Office607 DaysField of Search438/200, 438/230, 438/231, 438/232, 438/275, 438/655, 438/664US Class Current438/200CPC Class CodesH01L 21/823835 silicided or salicided gate...H01L 27/0266 using field effect transist...
