Fabrication of semiconductor device having shallow junctions with tapered spacer in isolation region
First Claim
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1. A method for fabricating a semiconductor device having shallow junctions comprising:
- providing a semiconductor substrate having source and drain regions and polysilicon gate regions;
depositing selective silicon on the source and drain regions;
providing dopant into the source and drain regions forming shallow junctions;
forming first insulating sidewall spacers on sidewalls of the gate regions by thermal oxidation of exposed silicon creating taper-shaped isolation where the source and drain regions meet the gate regions;
forming second insulating spacers on the first insulating sidewall spacers; and
siliciding the top surfaces of the source and drain regions and polysilicon gate regions.
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Abstract
A semiconductor device having shallow junctions is provided by providing a semiconductor substrate having source and drain regions and polysilicon gate regions; depositing selective silicon on the source and drain regions; providing dopant into the source and drain regions forming shallow junctions; forming first insulating spacers on sidewalls of the gate regions; forming second insulating sidewall spacers on the first insulating spacers; and siliciding the top surfaces of the source and drain regions and polysilicon gate regions.
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Citations
18 Claims
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1. A method for fabricating a semiconductor device having shallow junctions comprising:
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providing a semiconductor substrate having source and drain regions and polysilicon gate regions; depositing selective silicon on the source and drain regions; providing dopant into the source and drain regions forming shallow junctions; forming first insulating sidewall spacers on sidewalls of the gate regions by thermal oxidation of exposed silicon creating taper-shaped isolation where the source and drain regions meet the gate regions; forming second insulating spacers on the first insulating sidewall spacers; and siliciding the top surfaces of the source and drain regions and polysilicon gate regions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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