Method for manufacturing DRAM capacitor

• US 5,998,260 A
• Filed: 04/06/1998
• Issued: 12/07/1999
• Est. Priority Date: 01/14/1998
• Status: Expired due to Fees

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Lin, Benjamin Szu-Min
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): CHEN, JACK S J
• Application Number:
  US09/055,685
• Time in Patent Office: 610 Days
• Field of Search: 438/239, 438/240, 438/253, 438/254, 438/241, 438/255, 438/256, 438/260, 438/396, 438/397, 438/398, 438/399, 438/964, 257/303, 257/304, 257/306, 257/309, 257/310
• US Class Current: 438/254
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/318 the storage electrode having multiple segments

Abstract

A method for forming a DRAM capacitor that uses a sacrificial layer to form a gear-teeth mold for producing a storage electrode having a highly increased surface area. The mold in a sacrificial layer is formed by first depositing alternating layers of two different insulating materials on a dielectric layer, and then patterning the sacrificial layer to form an opening using a conventional method. Next, a wet etching operation is performed using an etchant having a high etching selectivity between the two insulating layers. Hence, sunken slots are formed in the insulating layers that have a higher etching rate than its adjacent insulating layers, thus obtaining a gear teeth cross-sectional profile. Finally, the mold in the sacrificial layer is used for forming the storage electrode.

Claims

1. A method for manufacturing a DRAM capacitor comprising:

providing a substrate having a field effect transistor formed thereon, wherein the field effect transistor includes a source/drain region;

forming a first dielectric layer and then a second dielectric layer over the substrate;

patterning the second dielectric layer to form a first opening to expose the first dielectric layer;

forming a sacrificial layer over the patterned second dielectric layer and filling the first opening, wherein the sacrificial layer is composed of a plurality of alternately stacked first insulating layers and second insulating layers;

patterning the sacrificial layer to form a second opening exposing the first opening and a portion of the second dielectric layer enclosing the first opening, and then etching the first dielectric layer through the first opening to form a contact opening exposing the source/drain region;

performing an etching operation whose etching rate on the first insulating layers and the second insulating layers is different, so that a plurality of sunken regions are formed by etching a portion of one of the first and the second insulating layers of the sacrificial layer from a vertical sidewall of the second opening, and the sunken regions form a gear-teeth cavity;

forming a first conductive layer on a sidewall of the second opening, wherein the first conductive layer also fills the gear-teeth cavity of the sacrificial layer as well as the contact opening such that the first conductive layer is electrically coupled to the exposed source/drain region;

removing the sacrificial layer to expose the first conductive layer;

forming a dielectric film over an exposed surface of the first conductive layer; and

forming a second conductive layer over the dielectric film to serve as a cell electrode.

2. The method of claim 1, wherein the step of forming the first dielectric layer includes depositing silicon dioxide.

3. The method of claim 1, wherein the step of forming the first dielectric layer includes depositing borophosphosilicate glass.

4. The method of claim 1, wherein the first dielectric layer and the second dielectric layer are formed from different materials.

5. The method of claim 1, wherein the step of forming the second dielectric layer includes depositing silicon nitride.

6. The method of claim 1, wherein the patterning of the second dielectric layer includes an anisotropic etching operation.

7. The method of claim 1, wherein the first insulating layers and the second insulating layers are formed from different materials.

8. The method of claim 1, wherein the step of forming the first insulating layers include depositing borophosphosilicate glass.

9. The method of claim 1, wherein the step of forming the first insulating layers include depositing tetra-ethyl-ortho-silicate (TEOS) silicon oxide.

10. The method of claim 1, wherein the step of forming the second insulating layers include depositing borophosphosilicate glass.

11. The method of claim 1, wherein the step of forming the second insulating layers include depositing tetra-ethyl-ortho-silicate (TEOS) silicon oxide.

12. The method of claim 1, wherein the step of removing the sacrificial layer includes an isotropic etching operation.

13. The method of claim 1, wherein the step of removing the sacrificial layer includes using a solution such as a diluted hydrofluoric acid solution.

14. The method of claim 1, wherein the step of removing the sacrificial layer includes using a solution such as a buffered oxide etchant.

15. The method of claim 1, wherein the step of forming the first conductive layer and the second conductive layer includes a low-pressure chemical vapor deposition method.

16. The method of claim 1, wherein the step of forming the first conductive layer and the second conductive layer includes depositing polysilicon.

17. The method of claim 16, wherein step of forming the first conductive layer and the second conductive layer includes an impurities-doping operation.

18. The method of claim 1, wherein the step of forming the dielectric film includes depositing silicon nitride/silicon dioxide, silicon dioxide/silicon nitride/silicon dioxide, tantalum pentoxide, PZT or BST.

19. The method of claim 1, wherein the step of forming the first conductive layer comprises:

depositing a conformal conductive layer over the substrate; and

performing an planarization process on the conductive layer so as to expose the sacrificial layer.

20. A method for manufacturing a DRAM capacitor, wherein a substrate has a field effect transistor formed thereon, in which the field effect transistor includes a source/drain region, the method comprising:

forming a first dielectric layer and then a second dielectric layer over the substrate;

patterning the second dielectric layer to form a first opening to expose the first dielectric layer;

forming a sacrificial layer over the patterned second dielectric layer and filling the first opening, wherein the sacrificial layer is composed of a plurality of alternately stacked first insulating layers and second insulating layers;

patterning the sacrificial layer and the first dielectric layer to form a second opening that exposes a portion of the second dielectric layer, and a contact opening that exposes the source/drain region, respectively, wherein the second opening exposes the contact opening, and the second opening is wider than the contact opening, wherein the second opening and the contact opening are continuously formed in a single etching process;

forming a sacrificial layer over the second dielectric layer, wherein the sacrificial layer is composed of a plurality of alternately stacked first insulating layers and second insulating layers;

patterning the sacrificial layer to form an opening, which is wider than the contact opening so as to expose the contact opening that exposes the source/drain region;

performing a wet etching operation whose etching rate on the first insulating layers and the second insulating layers is different, so that a plurality of sunken regions are formed due to the different etching rate on the first insulating layers and the second insulating layers, and the sunken regions form a gear-teeth cavity on a sidewall of the second opening of the sacrificial layer;

forming a first conductive layer on the sidewall of the second opening of the sacrificial layer, wherein the first conductive layer also fills the gear-teeth cavity of the sacrificial layer as well as the contact opening such that the first conductive layer is electrically coupled to the exposed source/drain region;

removing the sacrificial layer to further expose the first conductive layer;

forming a dielectric film over an exposed surface of the first conductive layer; and

forming a second conductive layer over the dielectric film to serve as a cell electrode.

21. The method of claim 20, wherein the step of forming the first dielectric layer includes depositing silicon dioxide.

22. The method of claim 20, wherein the step of forming the first dielectric layer includes depositing borophosphosilicate glass.

23. The method of claim 20, wherein the first dielectric layer and the second dielectric layer are formed from different materials.

24. The method of claim 20, wherein the step of forming the second dielectric layer includes depositing silicon nitride.

25. The method of claim 20, wherein the patterning of the second dielectric layer includes an anisotropic etching operation.

26. The method of claim 20, wherein the first insulating layers and the second insulating layers are formed from different materials.

27. The method of claim 20, wherein the step of forming the first insulating layers include depositing borophosphosilicate glass.

28. The method of claim 20, wherein the step of forming the first insulating layers include depositing tetra-ethyl-ortho-silicate (TEOS) silicon oxide.

29. The method of claim 20, wherein the step of forming the second insulating layers include depositing borophosphosilicate glass.

30. The method of claim 20, wherein the step of forming the second insulating layers include depositing tetra-ethyl-ortho-silicate (TEOS) silicon oxide.

31. The method of claim 20, wherein the step of removing the sacrificial layer includes an isotropic etching operation.

32. The method of claim 20, wherein the step of removing the sacrificial layer includes using a solution such as a diluted hydrofluoric acid solution.

33. The method of claim 20, wherein the step of removing the sacrificial layer includes using a solution such as a buffered oxide etchant.

34. The method of claim 20, wherein the step of forming the first conductive layer and the second conductive layer includes a low-pressure chemical vapor deposition method.

35. The method of claim 20, wherein the step of forming the first conductive layer and the second conductive layer includes depositing polysilicon.

36. The method of claim 35, wherein step of forming the first conductive layer and the second conductive layer includes an impurities-doping operation.

37. The method of claim 21, wherein the step of forming the dielectric film includes depositing silicon nitride/silicon dioxide, silicon dioxide/silicon nitride/silicon dioxide, tantalum pentoxide, PZT or BST.