Method of forming a semiconductor structure having laterally merged body layer

• US 5,998,266 A
• Filed: 12/19/1996
• Issued: 12/07/1999
• Est. Priority Date: 12/19/1996
• Status: Expired due to Term

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: MagePower Semiconductor Corporation
• Inventors: So, Koon Chong
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US08/781,934
• Time in Patent Office: 1,083 Days
• Field of Search: 438/270, 438/271, 438/272, 438/268, 438/299, 438/301, 438/589, 438/430, 438/449, 438/451, 438/420, 438/545, 438/529, 438/527, 438/524, 438/530, 438/555, 257/330, 257/331, 257/332, 148/DIG. 126
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trenched gate MOSFET (metal oxide semiconductor field effect transistor) structure is fabricated via a novel process which includes the step of using a common mask serving the dual role as a mask for the body layer formation and as a mask for trench etching. The common mask defines an patterned oxide layer which includes a plurality of openings at a predetermined distance away from the scribe line of the MOSFET structure. During fabrication, material of the body layer is implanted through the openings of the patterned oxide layer. Thereafter, the implanted material is side-diffused and merged together under a drive-in cycle as one continuous body layer. Using the same patterned oxide layer as a shield, trenches are anisotropically etched in the substrate. The MOSFET structure as formed requires no separate mask for delineating the active body region away from the scribe line, resulting reduction of fabrication steps. The consequential benefits are lower manufacturing costs and higher production yields.

Claims

1. A method of forming a semiconductor structure, comprising the steps of:

(a) providing a semiconductor substrate having a major surface;

(b) disposing a masking layer having at least two openings above said major surface;

(c) depositing material in said substrate through said at least two openings;

(d) diffusing said material in said substrate downwardly and sidewardly so as to merge the material under each of said at least two openings together;

(e) etching said substrate through said openings by using an etchant which does not significantly etch said masking layer to form at least two cavities in said substrate under said at least two openings;

(f) lining said cavities with insulating material; and

(g) filling said cavities with conductive material.

2. The method as set forth in claim 1 wherein said step of lining said cavities with insulating material includes lining said cavities with silicon dioxide, and said step of filling said cavities with conductive material includes filling said cavities with polycrystalline silicon.

3. The method as set forth in claim 1 wherein said masking layer being a first masking layer, said method further comprising the steps of:

(e) removing said first masking layer from said major surface;

(f) disposing a second masking layer having at least one opening above said major surface; and

(g) forming a source layer in said substrate by depositing material of said source layer through said at least one opening of said second masking layer.

4. The method as set forth in claim 3 wherein said semiconductor structure being a field effect transistor structure having a source, a gate and a drain, wherein said source includes said source layer, said gate includes said conductive material in said cavities, and said drain includes said substrate.

5. The method as set forth in claim 1 wherein said step (a) includes providing said semiconductor substrate with a n-type conductivity, and said step (c) includes depositing material of a p-type conductivity through said at least two openings.

6. The method as set forth in claim 1 wherein said substrate includes a scribe line surrounding said semiconductor structure, and wherein step (b) further comprising the substep of disposing said at least two openings at predetermined distances away from the scribe line.

7. A method of forming a semiconductor cell array, comprising the steps of:

(a) providing a semiconductor substrate of a first conductivity type, said substrate having a major surface;

(b) disposing a masking layer having a plurality of openings above said major surface;

(c) depositing material of a second conductivity type through said plurality of openings;

(d) diffusing material of said second conductivity type in said substrate sidewardly and downwardly so as to merge the material of said second conductivity type under each of said openings together;

(e) etching said substrate through the openings of said masking layer to form a plurality of trenches in said substrate;

(f) lining said trenches with insulating material; and

(g) filling said trenches with conductive material.

8. The method as set forth in claim 7 wherein said masking layer being a first masking layer, said method further comprising the steps of:

(h) removing said first masking layer from said major surface;

(i) disposing a second masking layer having a plurality of openings above said major surface; and

(j) forming a layer of said first conductivity type in said layer of said second conductivity type by depositing material of said first conductivity type through the openings of said second masking layer.

9. The method as set forth in claim 8 wherein said semiconductor cell array being an array of field effect transistors having a common source, a common drain and a common gate, wherein said common source includes said diffusion layer of said first conductivity type formed in step (j), said common drain includes said semiconductor substrate, and said common gate include said conductive material in said trenches formed in step (g).

10. The method as set forth in claim 9 further including the step of assigning said trenches as active trenches by electrically connecting the conductive material in said active trenches to said common gate, and as inactive trenches by electrically isolating the conductive material in said inactive trenches from said common gate.

11. The method as set forth in claim 10 wherein said substrate includes a scribe line surrounding said cell array, and wherein step (b) further comprising the substep of disposing said openings at predetermined distances away from said scribe line.