Fabrication of semiconductor device having shallow junctions

• US 5,998,273 A
• Filed: 01/25/1999
• Issued: 12/07/1999
• Est. Priority Date: 01/25/1999
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Ma, William Hsioh-Lien, Wann, Hsing-Jen C.
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): Pham, Long
• Application Number:
  US09/236,690
• Time in Patent Office: 316 Days
• Field of Search: 438/538, 438/305, 438/306, 438/307, 438/FOR 204, 438/300
• US Class Current: 438/305
• CPC Class Codes: H01L 21/2257 the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
• CPC Class Codes: H01L 21/28052 the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer formed by metal ion implantation H01L21/28044
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location

Abstract

A semiconductor device having shallow junctions is provided by providing a semiconductor substrate having source and drain regions and polysilicon gate regions; depositing selective silicon on the source and drain regions and on the polysilicon gate regions; providing dopant into the source and drain regions forming shallow junctions; forming first insulating spacers on sidewalls of the gate regions; forming second insulating sidewall spacers on the first insulating spacers; implanting dopants into the source and drain regions for providing deep junctions and into the polysilicon gate regions; and siliciding the top surfaces of the source and drain regions and polysilicon gate regions.

Claims

1. A method for fabricating a semiconductor device having shallow junctions comprising:

providing a semiconductor substrate having source and drain regions and polysilicon gate regions;

selectively depositing silicon on the source and drain regions and on the polysilicon gate regions;

providing a dopant into the source and drain regions to form shallow junctions;

forming first insulating sidewall spacers on sidewalls of the gate regions;

forming second insulating spacers on the first insulating sidewall spacers;

implanting dopants through the silicon into the source and drain regions for providing deep junctions, and into the polysilicon gate regions; and

siliciding top surfaces of the source and drain regions and polysilicon gate regions.

2. The method of claim 1 wherein the deposited silicon is doped and the shallow junctions are formed by driving in dopant from the selective silicon into the source and drain regions.

3. The method of claim 2 which comprises employing a short rapid thermal anneal for driving in the dopant.

4. The method of claim 3 wherein the short rapid thermal anneal is carried out at temperatures of about 800 to about 1200 for about 0.05 to about 1 minute.

5. The method of claim 1 wherein the deposited silicon is undoped and the shallow junctions are formed by implanting dopant ions into the source and drain regions.

6. The method of claim 1 wherein the shallow junctions are less than 200 Å

.

7. The method of claim 1 wherein the shallow junctions are about 50 to about 150 Å

.

8. The method of claim 1 wherein first insulating sidewall spacers are formed by thermal oxidation of the silicon and a polycrystalline silicon creating taper-shaped isolation where the source and drain regions meet the gate regions.

9. The method of claim 8 wherein the first insulating sidewall spacers are about 20 to about 100 Å

thick.

10. The method of claim 1 wherein the second insulating sidewall spacers are selected from the group consisting of silicon dioxide, silicon nitride, silicon oxynitride and mixtures thereof.

11. The method of claim 10 wherein the second insulating sidewall spacers are about 500 to about 2000 Å

thick.

12. The method of claim 1 wherein said siliciding comprising using a silicide forming metal selected from the group consisting of tungsten, titanium, cobalt, nickel and mixtures thereof.

13. The method of claim 1 which further comprises gate insulation between the substrate and the gate regions.

14. The method of claim 1 which further comprises providing sidewall insulating layers on sidewalls of the gate regions prior to depositing the selective silicon layer.

15. The method of claim 14 which further comprises removing the sidewall insulating layer after forming the shallow junctions and prior to forming the first insulating sidewall spacers.

16. The method of claim 15 wherein the sidewall insulating layer is about 10 to about 300 Å

thick.