Method of forming a multiple implant lightly doped drain (MILDD) field effect transistor

• US 5,998,274 A
• Filed: 10/14/1998
• Issued: 12/07/1999
• Est. Priority Date: 04/10/1997
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Akram, Salman, Ditali, Akram
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): Blum, David S
• Application Number:
  US09/172,439
• Time in Patent Office: 419 Days
• Field of Search: 438/231, 438/302, 438/306, 438/257, 438/297, 438/305, 438/274, 251/335
• US Class Current: 438/306
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A multiple implant lightly doped drain ("MILDD") field effect transistor is disclosed. The transistor includes a channel, a gate, a dielectric structure that separates the gate from the channel, a source region and a drain region. The drain region has a first drain subregion, a second drain subregion and a third drain subregion. Each drain subregion has a dopant concentration that differs from that of the other two drain subregions. A method of forming the same is also disclosed.

Claims

1. A method of forming a transistor on a substrate, comprising the following steps:

forming a dielectric layer overlying the substrate;

forming a gate structure overlying the dielectric layer, the gate structure having a first sidewall and a second sidewall, whereby a first contact region, a channel region and a second contact region are defined within the substrate;

forming first and second contact subregions within the second contact region, each contact subregion having a dopant concentration that differs from that of the other contact subregion; and

forming an anti-punchthrough region underlying the second contact region, wherein the step of forming the anti-punchthrough region comprises the step of forming a first anti-punchthrough subregion and the step of forming a second anti-punchthrough subregion, wherein the first anti-punchthrough subregion is formed below and in alignment with the first contact subregion, and wherein the second anti-punchthrough subregion is formed below and in alignment with the second contact subregion, each anti-punchthrough subregion having a dopant concentration that differs from that of the other anti-punchthrough subregion.

2. A method of forming a transistor on a substrate, comprising the following steps:

forming a dielectric layer overlying the substrate;

forming a gate structure overlying the dielectric layer, the gate structure having a first sidewall and a second sidewall, whereby a first contact region, a channel region and a second contact region are defined within the substrate;

forming first, second and third contact subregions within the second contact region, each contact subregion having a dopant concentration that differs from that of the other two contact subregions; and

forming an anti-punchthrough region underlying the second contact region, wherein the step of forming the anti-punchthrough region comprises the step of forming a first anti-punchthrough subregion, the step of forming a second anti-punchthrough subregion, and the step of forming a third anti-punchthrough subregion, wherein the first anti-punchthrough subregion is formed below and in alignment with the first contact subregion, the second anti-punchthrough subregion is formed below and in alignment with the second contact subregion, and the third anti-punchthrough subregion is formed below and in alignment with the third contact subregion, each anti-punchthrough subregion having a dopant concentration that differs from that of the other two anti-punchthrough subregions.