Method of reducing charging damage to integrated circuits in ion implant and plasma-based integrated circuit process equipment
First Claim
1. A method of reducing charging damage to integrated circuits during fabrication of integrated circuit die in a semiconductor wafer, each die being spaced from adjacent die by scribe lanes surrounding the die, the method comprising the step ofprocessing the scribe lanes during wafer processing to facilitate the flow of current to and from the wafer substrate during integrated circuit fabrication and reduce current flow through integrated circuit components and to reduce voltage between a surface of the integrated circuits and the wafer.
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Abstract
Charging damage to integrated circuits during ion implantation and plasma processing of integrated circuit die in a semiconductor wafer is reduced by processing scribe lanes during wafer fabrication to facilitate the flow of current to and from the wafer substrate through the scribe lanes during integrated circuit fabrication and reduce current flow through integrated circuit components.
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Citations
14 Claims
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1. A method of reducing charging damage to integrated circuits during fabrication of integrated circuit die in a semiconductor wafer, each die being spaced from adjacent die by scribe lanes surrounding the die, the method comprising the step of
processing the scribe lanes during wafer processing to facilitate the flow of current to and from the wafer substrate during integrated circuit fabrication and reduce current flow through integrated circuit components and to reduce voltage between a surface of the integrated circuits and the wafer.
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13. A method of reducing charging damage to integrated circuits during fabrication of integrated circuit die in a semiconductor wafer, each die being spaced from adjacent die by scribe lanes surrounding the die, the method comprising the step of
processing the semiconductor wafer to form current shunt paths within each die to reduce voltage between a surface of the integrated circuits and the wafer and reduce the potential across gate oxides of transistors in the integrated circuits.
Specification