Method of reducing charging damage to integrated circuits in ion implant and plasma-based integrated circuit process equipment

• US 5,998,282 A
• Filed: 10/21/1997
• Issued: 12/07/1999
• Est. Priority Date: 10/21/1997
• Status: Expired due to Fees

• Current Assignee: Wieslaw A. Lukaszek
• Original Assignee: Wieslaw A. Lukaszek
• Inventors: Lukaszek, Wieslaw A.
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Jones, Josetta I.
• Application Number:
  US08/955,162
• Time in Patent Office: 777 Days
• Field of Search: 438/460, 438/466, 438/462
• US Class Current: 438/460
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/321 After treatment

Abstract

Charging damage to integrated circuits during ion implantation and plasma processing of integrated circuit die in a semiconductor wafer is reduced by processing scribe lanes during wafer fabrication to facilitate the flow of current to and from the wafer substrate through the scribe lanes during integrated circuit fabrication and reduce current flow through integrated circuit components.

Claims

1. A method of reducing charging damage to integrated circuits during fabrication of integrated circuit die in a semiconductor wafer, each die being spaced from adjacent die by scribe lanes surrounding the die, the method comprising the step of

processing the scribe lanes during wafer processing to facilitate the flow of current to and from the wafer substrate during integrated circuit fabrication and reduce current flow through integrated circuit components and to reduce voltage between a surface of the integrated circuits and the wafer.

2. The method as defined by claim 1 wherein the processing includes masking the scribe lanes during ion implantation of doped wells within each die to prevent P-N junction formation in the scribe lanes.

3. The method as defined by claim 1 wherein the processing includes masking scribe lanes during field oxide growth to prevent oxide formation in the scribe lanes.

4. The method as defined by claim 1 wherein the processing includes masking scribe lanes during gate oxide formation for transistors to prevent oxide formation in the scribe lanes.

5. The method as defined by claim 1 wherein the processing includes opening limited portions of scribe lanes to ion implant during first source/drain ion implantation.

6. The method as defined by claim 5 wherein the processing includes opening additional limited portions of scribe lanes to ion implantation during second source/drain ion implant where such additional limited portions of the scribe lanes are complementary to the first source/drain ion implant.

7. The method as defined by claim 1 wherein the processing includes selectively unmasking photo resist masked scribe lanes during contact etching.

8. The method as defined by claim 7 wherein the processing includes making contacts to scribe lanes during contact formation.

9. The method as defined by claim 8 wherein the processing includes forming metal lines in scribe lanes on contacts during metal patterning for the die.

10. The method as defined claim 1 wherein the processing includes etching portions of scribe lanes to form vias in the scribe lanes during via etching in the die.

11. The method as defined by claim 1 wherein the processing includes forming current shunt paths within each die during wafer processing.

12. The method as defined by claim 1 wherein the processing includes masking scribe lanes during ion implantation doped well within each die to prevent P-N junction formation in the scribe lanes, masking scribe lanes during field oxide growth to prevent oxide formation in the scribe lanes, and masking scribe lanes during gate oxide formation for transistors to prevent oxide formation in the scribe lanes.

13. A method of reducing charging damage to integrated circuits during fabrication of integrated circuit die in a semiconductor wafer, each die being spaced from adjacent die by scribe lanes surrounding the die, the method comprising the step of

processing the semiconductor wafer to form current shunt paths within each die to reduce voltage between a surface of the integrated circuits and the wafer and reduce the potential across gate oxides of transistors in the integrated circuits.

14. The method as described in claim 13 and further including

processing scribe lanes during wafer processing to facilitate the flow of current to and from the wafer during integrated circuit fabrication to further reduce voltage between a surface of the integrated circuits and the wafer and reduce the potential across gate oxides of transistors in the integrated circuits.