Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect

• US 5,998,293 A
• Filed: 04/28/1998
• Issued: 12/07/1999
• Est. Priority Date: 06/05/1996
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Dawson, Robert, Michael, Mark W., Brennan, William S., Fulford, H. Jim Jr., Bandyopadhyay, Basab, Hause, Fred N.
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): WHIPPLE, MATTHEW LAVERNE
• Application Number:
  US09/067,425
• Time in Patent Office: 588 Days
• Field of Search: 438/619, 438/622, 438/637, 438/672, 438/FOR 355
• US Class Current: 438/619
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An improved multilevel interconnect structure is provided. The interconnect structure includes pillars spaced from each other across a wafer. The pillars are placed between levels of interconnect or between an interconnect level and a semiconductor substrate. The pillars are spaced from each other by an air gap, such that each conductor within a level of interconnect is spaced by air from one another. Furthermore, each conductor within one level of interconnect is spaced by air from each conductor within another level of interconnect. Air gaps afford a smaller interlevel and intralevel capacitance within the multilevel interconnect structure, and a smaller parasitic capacitance value affords minimal propagation delay and cross-coupling noise of signals sent through the conductors. The air gaps are formed by dissolving a sacrificial dielectric, and the conductors are prevented from bending or warping in regions removed of sacrificial dielectric by employing anodization on not just the upper surfaces of each conductor, but the sidewalls as well. The upper and sidewall anodization provides a more rigid metal conductor structure than if merely the upper or sidewall surfaces were anodized. Accordingly, the pillars can be spaced further apart and yet provide all necessary support to the overlying conductors.

Claims

1. A method for forming a multilevel interconnect structure, comprising:

patterning a spaced plurality of coplanar first pillars spaced from each other across a semiconductor topography;

filling the spaced regions between the first pillars with a sacrificial material;

forming a via through a select one of said first pillars inside the outer perimeter of said first pillars;

filling said via with a conductive material to form a contact extending through a select one of said first pillars to said semiconductor topography;

patterning a spaced plurality of coplanar first conductors in a plane parallel to the plane formed by said first pillars, wherein the first conductors reside upon said first pillars, upon the select one of said first pillars having said contact, and upon said sacrificial material;

exposing said first conductors to an anodizing agent; and

removing said sacrificial material to form a multilevel interconnect structure having air gaps between said first pillars and air gaps between said first conductors in regions removed of said sacrificial material.

2. The method as recited in claim 1, wherein said filling the spaced region comprises spin on depositing a silicate material.

3. The method as recited in claim 1, wherein said filling the spaced region comprises spin on depositing a silicate material and thereafter heating the silicate material.

4. The method as recited in claim 1, wherein said filling the spaced region comprises spin on depositing a material comprising hydrogen silsesquioxane.

5. The method as recited in claim 1, wherein said filling the spaced region comprises spin on depositing methyl silsesquioxane.

6. The method as recited in claim 1, wherein said forming a via comprises sputter removing a lateral inside portion of the select one of said first pillars.

7. The method as recited in claim 1, wherein said filling said via comprises chemical vapor depositing a tungsten material.

8. The method as recited in claim 1, wherein said patterning said first conductors comprises sputter depositing a layer of aluminum and thereafter selectively removing portions of the aluminum layer.

9. The method as recited in claim 1, wherein said exposing said first conductor comprises subjecting said first conductor to a hydroxide solution.

10. The method as recited in claim 1, wherein said exposing said first conductor comprises subjecting the upper surface and opposed sidewall surfaces of an aluminum first conductor to an oxygen-bearing solution for forming approximately 200 angstroms of aluminum oxide on the upper and opposed sidewall surfaces.

11. The method as recited in claim 1, wherein said removing comprises exposing said sacrificial material in regions between said first conductors to hydrogen fluoride solution which removes substantially all of said sacrificial material.