Protection structures for the suppression of plasma damage

• US 5,998,299 A
• Filed: 12/09/1997
• Issued: 12/07/1999
• Est. Priority Date: 12/09/1996
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Krishnan, Srikanth
• Primary Examiner(s): Stinson, Frankie L.
• Assistant Examiner(s): OLSEN, ALLAN W
• Application Number:
  US08/987,728
• Time in Patent Office: 728 Days
• Field of Search: 438/132, 438/152, 438/155, 438/196, 438/207, 438/215, 438/218, 438/248, 438/273, 438/274, 438/281, 438/294, 438/314, 438/318, 438/324, 438/326, 438/333, 438/353, 438/361 , 438/391, 438/601, 438/668, 438/669, 438/694, 438/700, 438/706, 438/710, 438/719, 438/720, 438/733, 438/734, 438/737, 216/13, 216/18, 216/39, 216/67, 216/75, 216/79
• US Class Current: 438/694
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 28/92 made by patterning layers, e.g. by etching conductive layers

Abstract

Protection structures for suppressing plasma damage. Plasma damage is shown to occur primarily during a metal clear portion of a metal etch as opposed to also occurring during the overetch portion of the etch. The protection structures (202) provide a temporary connection between the metal layer (210) being etched and the substrate or a protection device during the clear portion of the etch. This temporary connection (202) is removed as the metal (210) is cleared.

Claims

1. A method for suppressing plasma damage to devices during an etch process comprising the steps of:

depositing a conductive layer;

forming a pattern over said conductive layer, said pattern including a portion having a plurality of lines spaced a distance on the order of a minimum design rule;

etching said conductive layer using said pattern, wherein a temporary connection is maintained in said conductive layer during the etch at a location below said portion of said pattern in order to dissipate charge, and wherein said temporary connection is automatically disconnected as material from said conductive layer is cleared between said plurality of lines.

2. The method of claim 1, wherein said conductive layer is a metal interconnect layer.

3. The method of claim 1, wherein said conductive layer comprises polysilicon.

4. The method of claim 1, wherein said distance is less than said minimum design rule.

5. The method of claim 1, wherein said distance is greater than said minimum design rule.

6. The method of claim 1, wherein said distance is approximately equal to said minimum design rule.

7. The method of claim 1, wherein said temporary connection is connected to a substrate.

8. The method of claim 1, wherein said temporary connection is connected to a device.

9. The method of claim 1, wherein said temporary connection is connected to a well region in a substrate.

10. The method of claim 1, wherein said temporary connection is connected to a MOS capacitor.

11. A method for suppressing plasma damage during an etch process comprising the steps of:

depositing a conductive layer;

forming a pattern over said conductive layer, said pattern comprising a regular portion and a transient fuse portion having one or more lines spaced a distance on the order of a minimum design rule, said transient fuse portion connected to said regular portion and designed so as to form a temporary connection in said conductive layer for dissipating excess charge;

etching said conductive layer in a reactor such that material from said conductive layer clears last between said lines of said transient fuse portion, wherein excess charge from said plasma is dissipated during the etch through said temporary connection until said temporary connection is automatically disconnected by said material clearing between said lines of said transient fuse portion.

12. The method of claim 11, wherein said conductive layer is a metal interconnect layer.

13. The method of claim 11, wherein said conductive layer comprises polysilicon.

14. The method of claim 11, wherein said distance is less than said minimum design rule.

15. The method of claim 11, wherein said distance is greater than said minimum design rule.

16. The method of claim 11, wherein said temporary connection is connected to a substrate.

17. The method of claim 11, wherein said temporary connection is connected to a protection device.

18. A method for suppressing plasma damage to devices during a metal etch comprising the steps of:

forming a first via through a dielectric layer to a bottom electrode;

filling said first via to form a sacrificial contact;

depositing a metal layer over said dielectric layer;

patterning said metal layer; and

etching said metal layer in a plasma reactor to form a plurality of closely spaced lines, wherein said sacrificial contact is located between two of said plurality of closely spaced lines to temporarily shunt excess charge, continuing said etching step until material from said metal layer is removed from between said plurality of closely spaced lines and a portion of said sacrificial contact is removed thus disconnecting said sacrificial contact from said plurality of closely spaced lines such that said sacrifical contact no longer shunts the excess charge.

19. The method of claim 18, wherein said bottom electrode a second via/contact.

20. The method of claim 18, wherein said bottom electrode is connected to substrate.

21. The method of claim 18, wherein said bottom electrode is a metal line connected to a substrate.

22. The method of claim 18, wherein said bottom electrode is a metal line connected to a device.

23. The method of claim 18, wherein said bottom electrode is a metal lines connected to a well region.

24. The method of claim 18, wherein said bottom electrode is a metal line connected to a MOS capacitor.

25. The method of claim 18, wherein one of said two plurality of closely spaced lines partially overlaps said sacrifical contact.