Semiconductor integrated circuit and a method of manufacturing the same

• US 5,998,822 A
• Filed: 11/25/1997
• Issued: 12/07/1999
• Est. Priority Date: 11/28/1996
• Status: Expired due to Term

• Current Assignee: Umc Japan
• Original Assignee: Nippon Steel Semiconductor Corporation (United Microelectronics Corporation)
• Inventors: Wada, Toshio
• Primary Examiner(s): Meier, Stephen D.
• Application Number:
  US08/978,429
• Time in Patent Office: 742 Days
• Field of Search: 257/296, 257/301
• US Class Current: 257/301
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/765 by field effect H01L21/76264 takes precedence
• CPC Class Codes: H10B 12/37 the capacitor being at least partially in a trench in the substrate

Abstract

Dielectric isolation in the bit-line direction is performed by a first trench filled with an insulator, dielectric isolation in the word-line direction is performed by a second trench filled with a conductive film serving as a field-shield electrode interposing an insulating film, and capacitors are formed on side walls of the second trench by the conductive film and a semiconductor substrate with the insulating film interposed therebetween. A high-density, large-scale DRAM is realized by combining the technologies of field-shield element isolation, trench element isolation, and side-wall capacitors in a trench. In this DRAM, the conductive film in a trench-capacitor structure serves as a field-shield electrode in a field-shield structure for dielectric isolation between memory cells. Since the capacitor forms a capacitance inside the semiconductor substrate on one side wall of the trench, high-density integration is possible. This further increases the density and the scale of a semiconductor integrated circuit.

Claims

1. A semiconductor integrated circuit in which a plurality of memory cells having transistors and capacitors are arranged in a matrix manner on one major surface of a semiconductor substrate, comprising:

a trench formed in said semiconductor substrate between said memory cells adjacent to each other; and

a conductive film filling said trench with an insulating film intervening, the insulating film covering inner wall of said trench,

wherein said conductive film is a field-shield electrode for dielectrically isolating said memory cells adjacent to each other across said trench, capacitively coupled with said semiconductor substrate in said memory cells at side-wall portions of said trench through said insulating film, and constituting said capacitors of said memory cells together with said semiconductor substrate and said insulating film.

2. A circuit according to claim 1, wherein said semiconductor substrate is constituted by a heavily doped silicon single-crystal substrate of one conductivity type and a lightly doped epitaxial layer of the same conductivity type formed on said silicon single-crystal substrate.

3. A circuit according to claim 2, wherein said trench has a depth to reach said silicon single-crystal substrate through said epitaxial layer.

4. A circuit according to claim 1, wherein

said memory cells are formed in intersections of bit lines extending in a row direction and word lines extending in a column direction and constitute a memory cell array, and

said trenches extend substantially parallel to said word lines, and said memory cells between said trenches are dielectrically isolated by other trenches extending substantially parallel to said bit lines and filled with an insulator.

5. A circuit according to claim 1, wherein a potential of said field-shield electrode is a potential of an external power-supply.

6. A circuit according to claim 1, wherein a potential of said field-shield electrode is a reference potential of an external power-supply.

7. A circuit according to claim 2, wherein a potential of said field-shield electrode is a potential of said silicon single-crystal substrate.

8. A circuit according to claim 2 further comprising,

conductive regions formed in said side-wall portions of said trench in said epitaxial layer, and

wherein said conductive regions are electrically connected to at least one of drains and sources of said transistors.

9. A circuit according to claim 8, wherein said conductive region is two-layer structure constituted by diffusion regions having different conductivity types.

10. A circuit according to claim 1, wherein side-wall surfaces of said trench are roughened surfaces.

11. A circuit according to claim 10, wherein said roughened surfaces are is formed by crystal grains of poly crystal silicon.

12. A circuit according to claim 10, wherein said semiconductor substrate is constituted by a heavily doped silicon single-crystal substrate of one conductivity type and a lightly doped epitaxial layer of the same conductivity type formed on said silicon single-crystal substrate.

13. A circuit according to claim 12, wherein said trench has a depth to reach said silicon single-crystal substrate through said epitaxial layer.

14. A circuit according to claim 10, wherein

said memory cells are formed at intersections of bit lines extending in a row direction and word lines extending in a column direction and constitute a memory cell array, and

said trenches extend substantially parallel to said word lines, and said memory cells between said trenches are dielectrically isolated by other trenches extending substantially parallel to said bit lines and filled with an insulator.

15. A circuit according to claim 10, wherein a potential of said field-shield electrode is a potential of an external power-supply.

16. A circuit according to claim 10, wherein a potential of said field-shield electrode is a reference potential of an external power-supply.

17. A circuit according to claim 12, wherein a potential of said field-shield electrode is a potential of said silicon single-crystal substrate.

18. A circuit according to claim 12 further comprising,

conductive regions formed in portions close to said side-wall portions of said trench in said epitaxial layer, and

wherein said conductive regions are electrically connected to at least one of drains and sources of said transistors.

19. A circuit according to claim 18, wherein said conductive region is two-layer structure constituted by diffusion regions having different conductivity types.