Power semiconductor devices having improved high frequency switching and breakdown characteristics

• US 5,998,833 A
• Filed: 10/26/1998
• Issued: 12/07/1999
• Est. Priority Date: 10/26/1998
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: North Carolina State University (University of North Carolina System)
• Inventors: Baliga, Bantval Jayant
• Primary Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US09/178,845
• Time in Patent Office: 407 Days
• Field of Search: 257/565, 257/328, 257/329, 257/330, 257/331, 257/332, 257/333, 257/334, 257/339, 257/488, 257/471, 257/476
• US Class Current: 257/329
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/095 the components being Schottky barrier gate field-effect transistors
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Integrated power semiconductor devices having improved high frequency switching performance, improved edge termination characteristics and reduced on-state resistance include GD-UMOSFET unit cells with upper trench-based gate electrodes and lower trench-based source electrodes. The use of the trench-based source electrode instead of a larger gate electrode reduces the gate-to-drain capacitance (C_GD) of the UMOSFET and improves switching speed by reducing the amount of gate charging and discharging current that is needed during high frequency operation.

Claims

1. A UMOSFET, comprising:

a semiconductor substrate;

a first trench in said substrate;

an insulated gate electrode in said first trench; and

a source electrode in said first trench, extending between said insulated gate electrode and a bottom of said first trench.

2. The UMOSFET of claim 1, wherein said substrate contains a graded-doped drift region therein.

3. The UMOSFET of claim 1, further comprising:

a second trench in said substrate, adjacent said first trench;

a first field plate insulating region lining said second trench; and

a field plate on said first field plate insulating region.

4. The UMOSFET of claim 3, further comprising:

a second field plate insulating region on a face of said substrate; and

a field plate extension on the second field plate insulating region and electrically connected to said field plate.

5. The UMOSFET of claim 4, wherein said field plate extension and said field plate are electrically connected to said gate electrode or said source electrode.

6. The UMOSFET of claim 1, further comprising a Schottky rectifying contact on said substrate, adjacent said first trench.

7. A vertical power device, comprising:

a trench in a semiconductor substrate;

a source region of first conductivity type in the semiconductor substrate;

an insulated first source electrode in and adjacent a bottom of said trench;

a second source electrode on the substrate, electrically coupled to said source region and said insulated first source electrode; and

an insulated gate electrode in and adjacent a top of said trench.

8. The device of claim 7, wherein said trench has first and second opposing sidewalls;

and wherein said second source electrode forms an ohmic contact with a portion of said source region extending adjacent the first sidewall and forms a Schottky rectifying contact with a portion of the semiconductor substrate extending adjacent the second sidewall.

9. The device of claim 7, further comprising:

a base region of second conductivity type in a portion of the semiconductor substrate extending adjacent a first sidewall of said trench; and

a breakdown shielding region of second conductivity type in a portion of the semiconductor substrate extending adjacent a second sidewall of said trench.

10. The device of claim 9, wherein said breakdown shielding region is more highly doped than said base region.

11. The device of claim 10, wherein said breakdown shielding region extends deeper into the semiconductor substrate than said base region.

12. The device of claim 9, wherein said breakdown shielding region extends adjacent the second sidewall of said trench.

13. The device of claim 12, wherein said breakdown shielding region extends deeper into the semiconductor substrate than said base region.

14. A field effect transistor, comprising:

a semiconductor substrate having first and second opposing faces;

a source region of first conductivity type in said substrate, adjacent the first face;

a drain region of first conductivity type in said substrate, adjacent the second face;

a drift region of first conductivity type in said substrate, said drift region forming a non-rectifying junction with said drain region;

a base region of second conductivity type in said substrate, said base region extending between said source region and said drift region and forming first and second P-N junctions therewith, respectively;

a first trench in said substrate at the first face, said first trench having a sidewall extending adjacent said drift region and said base region and a bottom extending adjacent said drain region;

a gate electrode in said first trench, extending opposite said base region;

a first source electrode in said first trench, said first source electrode extending between said gate electrode and the bottom of said first trench; and

an electrically insulating region in said first trench, said electrically insulating region extending along the sidewall of said first trench and between said gate electrode and said first source electrode.

15. The transistor of claim 14, wherein said drift region has a graded first conductivity type doping concentration therein which decreases in a direction from said drain region to said base region.

16. The transistor of claim 15, wherein said electrically insulating region includes a gate insulating region having a first thickness as measured between said gate electrode and the sidewall of said first trench, and a source insulating region having a second thickness as measured between said first source electrode and the sidewall of said first trench;

and wherein the second thickness is greater than the first thickness.

17. The transistor of claim 16, wherein the first thickness is less than about 750 Å

; and

wherein the second thickness is greater than about 1500 Å

.

18. The transistor of claim 16, further comprising:

a second trench in said substrate at the first face, adjacent said first trench;

a first field plate insulating region having a uniform thickness lining said second trench; and

a field plate in said second trench, on said first field plate insulating region.

19. The transistor of claim 18, further comprising:

a second field plate insulating region on the first face; and

a field plate extension on the second field plate insulating region, opposite the first face.

20. The transistor of claim 19, wherein said field plate extension and said field plate are electrically connected together and are electrically connected to said gate electrode or said first source electrode.

21. The transistor of claim 18, wherein said first and second trenches define a transition mesa region therebetween;

and wherein said transition mesa region comprises a breakdown shielding region of second conductivity type therein which forms a third P-N junction with said drift region.

22. The transistor of claim 21, further comprising a second source electrode on the first face, ohmically contacting said source region;

and wherein said first and second source electrodes are electrically connected together and to said break down shielding region .

23. The transistor of claim 22, wherein said transition mesa region is devoid of a source region of first conductivity type therein.

24. The transistor of claim 22, wherein a distance between the first face and the third P-N junction is greater than a distance between the first face and the second P-N junction.

25. The transistor of claim 24, wherein said breakdown shielding region is more highly doped than said base region.

26. The transistor of claim 16, wherein the bottom of said trench defines an interface between said electrically insulating region and said drain region.

27. The transistor of claim 15, further comprising a second source electrode on the first face, ohmically contacting said source region;

and wherein said first and second source electrodes are electrically connected together.

28. The transistor of claim 15, wherein the first conductivity type doping concentration in said drift region is less than about 5×

10¹⁶ cm^-3 at the second P-N junction; and

wherein the first conductivity type doping concentration in said drift region is greater than about 5×

10¹⁶ cm^-3 at the non-rectifying junction.

29. The transistor of claim 28, wherein the second conductivity type doping concentration in said base region is greater than about 5×

10¹⁶ cm^-3 at the first P-N junction; and

wherein the first conductivity type doping concentration in said drift region at the non-rectifying junction is greater than the second conductivity type doping concentration in said base region at the first P-N junction.

30. The transistor of claim 28, wherein the second conductivity type doping concentration in said base region at the first P-N junction is about ten times greater than the first conductivity type doping concentration in said drift region at the second P-N junction.

31. The transistor of claim 14, wherein said electrically insulating region includes a gate insulating region having a first thickness as measured between said gate electrode and the sidewall of said first trench, and a source insulating region having a second thickness as measured between said first source electrode and the sidewall of said first trench;

and wherein the second thickness is greater than the first thickness.

32. The transistor of claim 14, further comprising a second source electrode on the first face, ohmically contacting said source region;

and wherein said first and second source electrodes are electrically connected together.

33. The transistor of claim 14, further comprising:

a second trench in said substrate at the first face, adjacent said first trench;

a first field plate insulating region lining said second trench; and

a field plate on said first field plate insulating region.

34. The transistor of claim 33, further comprising:

a second field plate insulating region on the first face; and

a field plate extension on the second field plate insulating region, opposite the first face.

35. The transistor of claim 34, wherein said field plate extension and said field plate are electrically connected together and are electrically connected to said gate electrode or said first source electrode.

36. A semiconductor switching device, comprising:

a semiconductor substrate having first and second opposing faces;

a drain region of first conductivity type in said substrate, adjacent the second face;

a drift region of first conductivity type in said substrate, said drift region forming a non-rectifying junction with said drain region;

a trench in said substrate at the first face, said trench having first and second opposing sidewalls which extend into said drift region;

a source region of first conductivity type in said substrate, said source region extending opposite the first sidewall of said trench and adjacent the first face;

a base region of second conductivity type in said substrate, said base region extending between said source region and said drift region and forming first and second P-N junctions therewith, respectively;

a gate electrode insulating region lining the first and second sidewalls of said trench;

a gate electrode in said trench, on said gate electrode insulating region;

a Schottky contact adjacent the first face, said Schottky contact forming a Schottky rectifying junction with a portion of said drift region extending opposite the second sidewall of said trench;

a first source electrode disposed between said gate electrode and a bottom of said trench; and

a second source electrode on the first face, ohmically contacting said source region.

37. The device of claim 36, wherein said drift region has a graded first conductivity type doping concentration therein which decreases in a direction from said drain region to said base region.

38. The device of claim 37, wherein said drift region includes a uniformly doped region of first conductivity type therein extending adjacent the first face;

and wherein said Schottky contact forms a Schottky rectifying junction with said uniformly doped region.

39. The device of claim 38, wherein a thickness of said gate electrode insulating region as measured between said gate electrode and said base region is less than about 750 Å

; and

wherein a thickness of said gate electrode insulating region as measured between said gate electrode and said drift region is greater than about 1500 Å

.

40. The device of claim 37, wherein a bottom of said trench defines an interface between said gate electrode insulating region and said drain region.

41. A semiconductor switching device, comprising:

a semiconductor substrate having first and second opposing faces;

a drain region of first conductivity type in said substrate, adjacent the second face;

a drift region of first conductivity type in said substrate, said drift region forming a non-rectifying junction with said drain region;

a trench in said substrate at the first face, said trench having first and second opposing sidewalls which extend into said drift region;

a source region of first conductivity type in said substrate, said source region extending opposite the first sidewall of said trench and adjacent the first face;

a base region of second conductivity type in said substrate, said base region extending between said source region and said drift region and forming first and second P-N junctions therewith, respectively, which extend to the first sidewall;

a gate electrode in said trench; and

a gate electrode insulating region lining the first and second sidewalls of said trench, said gate electrode insulating region having a first thickness less than about 750 Å

as measured between said gate electrode and a first intersection between the first sidewall and the first P-N junction and a second thickness greater than about 1500 Å

as measured between said gate electrode and a second intersection between the first sidewall and the second P-N junction.

42. The device of claim 41, further comprising a Schottky contact adjacent the first face, said Schottky contact forming a Schottky rectifying junction with a portion of said drift region extending opposite the second sidewall of said trench.

43. The device of claim 42, wherein said drift region has a graded first conductivity type doping concentration therein which decreases in a direction from said drain region to said base region.

44. The device of claim 43, wherein said drift region includes a uniformly doped region of first conductivity type therein extending adjacent the first face;

and wherein said Schottky contact forms a Schottky rectifying junction with said uniformly doped region.

45. The device of claim 44, wherein a bottom of said trench defines an interface between said gate electrode insulating region and said drain region.