Trench-gated power MOSFET with protective diode

• US 5,998,836 A
• Filed: 04/30/1997
• Issued: 12/07/1999
• Est. Priority Date: 06/02/1995
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Williams, Richard K.
• Primary Examiner(s): Jackson, Jr., Jerome
• Application Number:
  US08/846,688
• Time in Patent Office: 951 Days
• Field of Search: 257/328, 257/331, 257/341, 257/409
• US Class Current: 257/341
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A power MOSFET includes a trenched gate which defines a plurality of MOSFET cells. A protective diffusion is created, preferably in an inactive cell, so as to form a diode that is connected in parallel with the channel region in each of the MOSFET cells. The protective diffusion, which replaces the deep central diffusion taught in U.S. Pat. No. 5,072,266, prevents impact ionization and the resulting generation of carriers near the corners of the gate trench, which can damage or rupture the gate oxide layer. Moreover, the diode can be designed to have a breakdown voltage which limits the strength of the electric field across the gate oxide layer. The elimination of a deep central diffusion permits an increase in cell density and improves the on-resistance of the MOSFET.

Claims

1. A trench-gated vertical power MOSFET comprising:

a semiconductor chip, said chip comprising a drain region of a first conductivity type;

a gate positioned in a trench formed in a surface of said semiconductor chip, said trench defining a two-dimensional array of cells, each of said cells being in the shape of a closed figure and being surrounded on all sides by said trench, each cell in a first group of said cells comprising a MOSFET cell and each cell in a second group of said cells comprising a diode cell, each of said MOSFET cells comprising;

a source region of said first conductivity type and a body region of a second conductivity type adjoining said source region, said body region comprising a channel region adjacent a side of said trench, said channel region being for conducting a current between said source and drain regions when said power MOSFET is turned on;

each of said diode cells comprising;

a protective diffusion of said second conductivity type, said protective diffusion forming a junction with said drain region so as to form a diode, said diode being connected in parallel with said channel region in each of said MOSFET cells, said diode cell containing no channel region adjacent a side of said trench; and

wherein said diode cells are distributed at repetitive intervals in said two-dimensional array, there being a predetermined number of MOSFET cells for every diode cell in said array, said diode cells being positioned in said array so as to limit the strength of an electric field and the formation of hot carriers in the vicinity of said trench throughout said array.

2. The MOSFET of claim 1 wherein said semiconductor chip comprises a substrate and an epitaxial layer formed on a surface of said substrate, said substrate having a greater doping concentration than said epitaxial layer.

3. The MOSFET of claim 2 wherein a bottom of said trench is located in said epitaxial layer and is separated from an interface between said substrate and said epitaxial layer.

4. The MOSFET of claim 3 wherein a bottom of said protective diffusion is located in said epitaxial layer and is separated from said interface between said substrate and said epitaxial layer.

5. The MOSFET of claim 4 wherein said protective diffusion is shorted to the source region of each of said MOSFET cells.

6. The MOSFET of claim 2 wherein a bottom of said trench is located in said substrate.

7. The MOSFET of claim 6 wherein a bottom of said protective diffusion is located at an interface between said substrate and said epitaxial layer.

8. The MOSFET of claim 6 wherein a region of said first conductivity in said epitaxial layer separates said body region from said substrate in said MOSFET cells.

9. The MOSFET of claim 1 wherein said trench forms a lattice of square cells.

10. The MOSFET of claim 1 wherein said trench forms a lattice of cells in the form of stripes.

11. The MOSFET of claim 6 wherein said gate is separated from said semiconductor chip by a gate oxide layer, and wherein said diode has a breakdown voltage that is lower than a voltage that causes damage to said gate oxide layer.

12. The MOSFET of claim 8 wherein a region of said first conductivity in said epitaxial layer separates said protective diffusion from said substrate in said diode cell.

23. The MOSFET of claim 6 wherein a PN junction between said body region and said drain region in said MOSFET cells is located above an interface between said epitaxial layer and said substrate.

24. The MOSFET of claim 23 wherein a PN junction between said protective diffusion and said drain region is coincident with said interface between said epitaxial layer and said substrate.

25. The MOSFET of claim 23 wherein a portion of said MOSFET cells between said PN junction and said interface is doped with material of said first conductivity type.

26. The MOSFET of claim 23 wherein a portion of said MOSFET cells between said PN junction and said interface is doped with material of said second conductivity type.

27. The MOSFET of claim 6 wherein a PN junction between said body region and said drain region in said MOSFET cells is coincident with an interface between said epitaxial layer and said substrate.

13. A trench-gated power MOSFET comprising:

a semiconductor chip comprising an epitaxial layer overlying a substrate, said substrate having a greater doping concentration than said epitaxial layer;

a trench formed in said epitaxial layer and extending through said epitaxial layer and into said substrate, a gate being formed in said trench and separated by an oxide layer from said substrate, said trench defining a lattice, said lattice defining a plurality of MOSFET cells, each of said MOSFET cells comprising a source region of a first conductivity type and a body region of a second conductivity type adjoining said source region, said source region and said body region abutting a side of said trench, said body region comprising a channel region for conducting a current when said MOSFET is turned on;

wherein said body region adjoins a drain region of said first conductivity type, a PN junction between said body region and said drain region forming a diode, said diode having a breakdown voltage that is less than or equal to 4 megavolts/centimeter multiplied by a thickness of said oxide layer at a bottom of said trench, said thickness being expressed in centimeters.

14. The MOSFET of claim 13 wherein said body region is shorted to said source region in each of said MOSFET cells.

18. The MOSFET of claim 13 wherein said source and body regions in each of said MOSFET cells are formed in said epitaxial layer.

22. The MOSFET of claim 13 further comprising a contact region of said second conductivity type abutting said body region and adjacent a surface of said epitaxial layer, said contact region being doped more heavily than said body region, said contact region, said substrate, and a portion of said body region between said contact region and said substrate forming a PIN diode, said PIN diode having a breakdown voltage that is less than or equal to 4 megavolts/centimeter multiplied by a thickness of said oxide layer at a bottom of said trench, said thickness being expressed in centimeters.

15. A vertical power semiconductor switch comprising a semiconductor substrate, a first terminal of said switch being located adjacent a top side of said substrate and a second terminal of said switch being located adjacent a back side of said substrate, a trench being formed in a surface of said substrate and containing a gate, said trench being in the form of a lattice and defining a two-dimensional array comprising a plurality of MOSFET cells and a plurality of diode cells, each of said MOSFET and diode cells being in the form of a closed figure and being surrounded on all sides by said trench, each of said MOSFET cells containing a MOSFET, each of said diode cells containing a diode but no MOSFET, said diode cells being positioned at predetermined locations in said two-dimensional array such that said diode cells break down and protect said MOSFET cells from damage arising from a voltage applied between said first and second terminals when said switch is turned off.

16. The power semiconductor switch of claim 15 wherein each of said MOSFETs is connected in parallel with each of said diodes.

17. The power semiconductor switch of claim 16 wherein each of said diodes is connected such that a forward direction of current flow through said diodes is opposite to a normal direction of current flow between said first and second terminals.

19. The power semiconductor switch of claim 15 wherein said diode cells are positioned in a repetitive pattern within said two-dimensional array.

20. The power semiconductor switch of claim 19 wherein there are subgroups of cells within said two-dimensional array, each subgroup containing n cells, m cells in said subgroup comprising diode cells and n-m cells within said subgroup comprising MOSFET cells.

21. A trench gated vertical MOSFET comprising:

a semiconductor chip, said chip comprising a drain region of a first conductivity type;

a gate positioned in a trench formed in a surface of said semiconductor chip, said trench defining an array of MOSFET cells and diode cells, each of said MOSFET cells comprising;

a source region of said first conductivity type; and

a body region of a second conductivity type adjoining said source region, said body region comprising a channel region adjacent a side of said trench, said channel region being for conducting a current between said source and drain regions when said MOSFET is turned on;

said MOSFET cells comprising a first group of cells and a second group of cells, the cells in said second group being larger than the cells in said first group, said body region in said first group being located entirely above a level of a bottom of said trench, the cells in said second group comprising a protective deep body diffusion such that a portion of said body region extends below said level of the bottom of said trench.