Semiconductor device including active matrix circuit

• US 5,998,841 A
• Filed: 10/05/1998
• Issued: 12/07/1999
• Est. Priority Date: 06/13/1994
• Status: Expired due to Term

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Suzawa, Hideomi
• Primary Examiner(s): Ngo, Ngan V.
• Application Number:
  US09/166,157
• Time in Patent Office: 428 Days
• Field of Search: 257/59, 257/71, 257/72, 257/350, 257/351, 257/296, 257/379
• US Class Current: 257/350
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

There is provided a combination of doping process and use of side walls which allows the source and drain of a thin film transistor of an active matrix circuit to be doped with only one of N-type and P-type impurities and which allows the source and drain of a thin film transistor used in a peripheral circuit of the same conductivity type as that of the thin film transistor of the active matrix circuit to include both of N-type and P-type impurities. Also, a thin film transistor in an active matrix circuit has offset regions by using side walls, and another thin film transistor in a peripheral circuit has a lightly doped region by using side walls.

Claims

1. A semiconductor device comprising at least an active matrix region and a peripheral circuit,

(a) said active matrix region comprising:

a semiconductor island formed over a substrate;

at least first and second thin film transistors formed with said semiconductor island, each of which includes a channel region in said semiconductor island and a gate electrode adjacent to said channel region;

a signal line bormed over said substrate and connected to said first thin film transistor;

a pixel electrode connected to said second thin film transistor wherein said first and second thin film transistors are connected in series between said signal line and said pixel electrode; and

a capacitor forming electrode formed adjacent to a potion of said semiconductor island to form a capacitor therebetween, and

(b) said peripheral circuit comprising;

at least one CMOS circuit comprising a pair of an N-channel thin film transistor and a P-channel thin film transistor over said substrate, each of said an N-channel thin film transistor and a P-channel thin film transistor comprising;

a semiconductor island over said substrate, said semiconductor island having a channel region, and source and drain regions;

a gate insulating film adjacent to said semiconductor island; and

a gate electrode adjacent to said semiconductor island with said gate insulating film interposed therebetween,

wherein said semiconductor island of at least said N-channel thin transistor comprises a pair of LDD regions between said channel region and said source and drain regions.

2. A semiconductor device comprising at least an active matrix region and a peripheral circuit,

(a) said active matrix region comprising:

a semiconductor island formed over a substrate;

at least first and second thin film transistors formed with said semiconductor island, each of which includes a channel region in said semiconductor island and a gate electrode over said channel region;

a signal line formed over said substrate and connected to said first thin film transistor;

a pixel electrode connected to said second thin film transistor wherein said first and second thin film transistors are connected in series between said signal line and said pixel electrode; and

a capacitor forming electrode formed over a potion of said semiconductor island to form a capacitor therebetween, and

(b) said peripheral circuit comprising;

at least one CMOS circuit comprising a pair of an N-channel thin film transistor and a P-channel thin film transistor over said substrate, each of said an N-channel thin film transistor and a P-channel thin film transistor comprising;

a semiconductor island over said substrate, said semiconductor island having a channel region, and source and drain regions;

a gate insulating film adjacent to said semiconductor island; and

a gate electrode over said semiconductor island with said gate insulating film interposed therebetween,

wherein said semiconductor island of at least said N-channel thin transistor comprises a pair of LDD regions between said channel region and said source and drain regions.

3. A semiconductor device comprising at least an active matrix region and a peripheral circuit,

(a) said active matrix region comprising:

a semiconductor island formed over a substrate;

at least first and second thin film transistors formed with said semiconductor island, each of which includes a channel region in said semiconductor island and a gate electrode adjacent to said channel region;

a signal line firmed over said substrate and connected to said first thin film transistor;

a pixel electrode connected to said second thin film transistor wherein said first and second thin film transistors are connected in series between said signal line and said pixel electrode;

a capacitor forming electrode formed adjacent to a potion of said semiconductor island to form a capacitor therebetween,

wherein a contact of said semiconductor island to said pixel electrode is located between said portion of the semiconductor island and said second thin film transistor;

(b) said peripheral circuit comprising;

at least one CMOS circuit comprising a pair of an N-channel thin film transistor and a P-channel thin film transistor over said substrate.

4. A semiconductor device comprising at least an active matrix region and a peripheral circuit,

(a) said active matrix region comprising:

a semiconductor island formed over a substrate;

at least first and second thin film transistors formed with said semiconductor island, each of which includes a channel region in said semiconductor island and a gate electrode over said channel region;

a signal line formed over said substrate and connected to said first thin film transistor;

a pixel electrode connected to said second thin film transistor wherein said first and second thin film transistors are connected in series between said signal line and said pixel electrode;

a capacitor forming electrode formed over a potion of said semiconductor island to form a capacitor therebetween,

wherein a contact of said semiconductor island to said pixel electrode is located between said portion of the semiconductor island and said second thin film transistor;

(b) said peripheral circuit comprising;

at least one CMOS circuit comprising a pair of an N-channel thin film transistor and a P-channel thin film transistor over said substrate.

5. A semiconductor device comprising at least an active matrix region and a peripheral circuit,

(a) said active matrix region comprising:

a semiconductor island formed over a substrate;

at least first and second thin film transistors formed with said semiconductor island, each of which includes a channel region and impurity regions in said semiconductor island and a gate electrode adjacent to said channel region;

a signal line formed over said substrate and connected to said first thin film transistor;

a pixel electrode connected to said second thin film transistor wherein said first and second thin film transistors are connected in series between said signal line and said pixel electrode;

a capacitor forming electrode formed adjacent to a potion of said semiconductor island to form a capacitor therebetween,

wherein said portion is surrounded by at least two of said impurity regions in said semiconductor island, and

(b) said peripheral circuit comprising;

at least one CMOS circuit comprising a pair of an N-channel thin film transistor and a P-channel thin film transistor over said substrate.

6. A semiconductor device comprising at least an active matrix region and a peripheral circuit,

(a) said active matrix region comprising:

a semiconductor island formed over a substrate;

at least first and second thin film transistors formed with said semiconductor island, each of which includes a channel region and impurity regions in said semiconductor island and a gate electrode over said channel region;

a signal line formed over said substrate and connected to said first thin film transistor;

a pixel electrode connected to said second thin film transistor wherein said first and second thin film transistors are connected in series between said signal line and said pixel electrode;

a capacitor forming electrode formed over a potion of said semiconductor island to form a capacitor therebetween,

wherein said portion is surrounded by at least two of said impurity regions in said semiconductor island, and

(b) said peripheral circuit comprising;

at least one CMOS circuit comprising a pair of an N-channel thin film transistor and a P-channel thin film transistor over said substrate.

7. A semiconductor device comprising at least an active matrix region and a peripheral circuit,

(a) said active matrix region comprising:

a semiconductor island formed over a substrate;

at least first and second thin film transistors formed with said semiconductor island, each of which includes a channel region in said semiconductor island and a gate electrode adjacent to said channel region;

a gate line formed over said substrate and connected to said gate electrodes of said fist and second thin transistors;

a signal line formed over said substrate and connected to said first thin film transistor;

a pixel electrode connected to said second thin film transistor wherein said first and second thin film transistors are connected in series between said signal line and said pixel electrode;

a capacitor forming electrode formed adjacent to a potion of said semiconductor island to form a capacitor therebetween,

wherein said gate line is parallel to said capacitor forming electrode in said active matrix region, and

(b) said peripheral circuit comprising;

at least one CMOS circuit comprising a pair of an N-channel thin film transistor and a P-channel thin film transistor over said substrate.

8. A semiconductor device comprising at least an active matrix region and a peripheral circuit,

(a) said active matrix region comprising:

a semiconductor island formed over a substrate;

at least first and second thin film transistors formed with said semiconductor island, each of which includes a channel region in said semiconductor island and a gate electrode over said channel region;

a gate line formed over said substrate and connected to said gate electrodes of said fist and second thin transistors;

a signal line formed over said substrate and connected to said first thin film transistor;

a pixel electrode connected to said second thin film transistor wherein said first and second thin film transistors are connected in series between said signal line and said pixel electrode;

a capacitor forming electrode formed over a potion of said semiconductor island to form a capacitor therebetween,

wherein said gate line is parallel to said capacitor forming electrode in said active matrix region, and

(b) said peripheral circuit comprising;

at least one CMOS circuit comprising a pair of an N-channel thin film transistor and a P-channel thin film transistor over said substrate.

9. A semiconductor device comprising at least an active matrix region and a peripheral circuit,

(a) said active matrix region comprising:

a semiconductor island formed over a substrate;

at least first and second thin film transistors formed with said semiconductor island, each of which includes a channel region in said semiconductor island and a gate electrode adjacent to said channel region;

a signal line formed over said substrate and connected to said first thin film transistor;

a pixel electrode connected to said second thin film transistor wherein said first and second thin film transistors are connected in series between said signal line and said pixel electrode;

a capacitor forming electrode formed adjacent to a potion of said semiconductor island to form a capacitor therebetween,

wherein said source line and said capacitor forming electrode cross at right angles in said active matrix region, and

(b) said peripheral circuit comprising;

at least one CMOS circuit comprising a pair of an N-channel thin film transistor and a P-channel thin film transistor over said substrate.

10. A semiconductor device comprising at least an active matrix region and a peripheral circuit,

(a) said active matrix region comprising:

a semiconductor island formed over a substrate;

at least first and second thin film transistors formed with said semiconductor island, each of which includes a channel region in said semiconductor island and a gate electrode over said channel region;

a signal line formed over said substrate and connected to said first thin film transistor;

a pixel electrode connected to said second thin film transistor wherein said first and second thin film transistors are connected in series between said signal line and said pixel electrode;

a capacitor forming electrode formed over a potion of said semiconductor island to form a capacitor therebetween,

wherein said source line and said capacitor forming electrode cross at right angles in said active matrix region, and

(b) said peripheral circuit comprising;

at least one CMOS circuit comprising a pair of an N-channel thin film transistor and a P-channel thin film transistor over said substrate.

11. A semiconductor device comprising at least an active matrix region and a peripheral circuit,

(a) said active matrix region comprising:

a semiconductor island on an insulating surface of a substrate, said semiconductor island comprising at least first and second channel regions, and a plurality of impurity regions;

a gate insulating film adjacent to said semiconductor island;

at least first and second gate electrodes adjacent to said first and second channel regions with said gate insulating film interposed therebetween, respectively;

a capacitor forming electrode adjacent to said semiconductor island with said gate insulating film interposed therebetween; and

a pixel electrode connected with said semiconductor island, and

(b) said peripheral circuit comprising;

at least one CMOS circuit comprising a pair of an N-channel thin film transistor and a P-channel thin film transistor on said insulating surface of said substrate, each of said an N-channel thin film transistor and a P-channel thin film transistor comprising;

a semiconductor island on said insulating surface of said substrate, said semiconductor island having a channel region, and source and drain regions;

a gate insulating film adjacent to said semiconductor island; and

a gate electrode adjacent to said semiconductor island with said gate insulating film interposed therebetween,

wherein said semiconductor island of at least said N-channel thin transistor comprises a pair of LDD repions located between said channel region and said source and drain regions, respectively.

12. A semiconductor device comprising at least an active matrix region and a peripheral circuit,

(a) said active matrix region comprising:

a semiconductor island on an insulating surface of a substrate, said semiconductor island comprising at least first and second channel regions, and a plurality of impurity regions;

a gate insulating film on said semiconductor island;

at least first and second gate electrodes over said first and second channel regions with said gate insulating film interposed therebetween, respectively;

a capacitor forming electrode over said semiconductor island with said gate insulating film interposed therebetween; and

a pixel electrode connected with said semiconductor island, and

(b) said peripheral circuit comprising;

at least one CMOS circuit comprising a pair of an N-channel thin film transistor and a P-channel thin film transistor on said insulating surface of said substrate, each of said an N-channel thin film transistor and a P-channel thin film transistor comprising;

a semiconductor island on said insulating surface of said substrate, said semiconductor island having a channel region, and source and drain regions;

a gate insulating film on said semiconductor island; and

a gate electrode over said semiconductor island with said gate insulating film interposed therebetween,

wherein said semiconductor island of at least said N-channel thin transistor comprises a pair of LDD regions between said channel region and said source and drain regions, respectively.

13. A semiconductor device comprising at least an active matrix region and a peripheral circuit,

(a) said active matrix region comprising:

a semiconductor island on an insulating surface of a substrate, said semiconductor island comprising at least first and second channel regions, and a plurality of impurity regions;

a gate insulating film adjacent to said semiconductor island;

at least first and second gate electrodes adjacent to said first and second channel regions with said gate insulating film interposed therebetween, respectively;

a capacitor forming electrode adjacent to said semiconductor island with said gate insulating film interposed therebetween; and

a pixel electrode connected with said semiconductor island,

wherein said pixel electrode is in contact with a region of said semiconductor island, said region located between a portion under said capacitor forming electrode and one of said impurity regions in said semiconductor island, and

(b) said peripheral circuit comprising;

at least one CMOS circuit comprising a pair of an N-channel thin film transistor and a P-channel thin film transistor on said insulating surface of said substrate.

14. A semiconductor device comprising at least an active matrix region and a peripheral circuit,

(a) said active matrix region comprising:

a semiconductor island on an insulating surface of a substrate, said semiconductor island comprising at least first and second channel regions, and a plurality of impurity regions;

a gate insulating film on said semiconductor island;

at least first and second gate electrodes over said first and second channel regions with said gate insulating film interposed therebetween, respectively;

a capacitor forming electrode over said semiconductor island with said gate insulating film interposed therebetween; and

a pixel electrode connected with said semiconductor island,

wherein said pixel electrode is in contact with a region of said semiconductor island, said region located between a portion under said capacitor forming electrode and one of said impurity regions in said semiconductor island, and

(b) said peripheral circuit comprising;

at least one CMOS circuit comprising a pair of an N-channel thin film transistor and a P-channel thin film transistor on said insulating surface of said substrate.

15. A semiconductor device comprising at least an active matrix region and a peripheral circuit,

(a) said active matrix region comprising:

a semiconductor island on an insulating surface of a substrate, said semiconductor island comprising at least first and second channel regions, and a plurality of impurity regions;

a gate insulating film adjacent to said semiconductor island;

at least first and second gate electrodes adjacent to said first and second channel regions with said gate insulating film interposed therebetween, respectively;

a capacitor forming electrode adjacent to a portion in said semiconductor island with said gate insulating film interposed therebetween; and

a pixel electrode connected with said semiconductor island,

wherein said portion is surrounded by at least two of said impurity regions in said semiconductor island, and

(b) said peripheral circuit comprising;

at least one CMOS circuit comprising a pair of an N-channel thin film transistor and a P-channel thin film transistor on said insulating surface of said substrate.

16. A semiconductor device comprising at least an active matrix region and a peripheral circuit,

(a) said active matrix region comprising:

a semiconductor island on an insulating surface of a substrate, said semiconductor island comprising at least first and second channel regions, and a plurality of impurity regions;

a gate insulating film on said semiconductor island;

at least first and second gate electrodes over said first and second channel regions with said gate insulating film interposed therebetween, respectively;

a capacitor forming electrode over a portion in said semiconductor island with said gate insulating film interposed therebetween; and

a pixel electrode connected with said semiconductor island,

wherein said portion is surrounded by at least two of said impurity regions in said semiconductor island, and

(b) said peripheral circuit comprising;

at least one CMOS circuit comprising a pair of an N-channel thin film transistor and a P-channel thin film transistor on said insulating surface of said substrate.

17. A semiconductor device comprising at least an active matrix region and a peripheral circuit,

(a) said active matrix region comprising:

a semiconductor island on an insulating surface of a substrate, said semiconductor island comprising at least first and second channel regions, and a plurality of impurity regions;

a gate insulating film adjacent to said semiconductor island;

at least first and second gate electrodes adjacent to said first and second channel regions with said gate insulating film interposed therebetween, respectively;

a gate line connected to said first and second gate electrodes;

a capacitor forming electrode adjacent to a portion in said semiconductor island with said gate insulating film interposed therebetween; and

a pixel electrode connected with said semiconductor island,

wherein said gate line is parallel to said capacitor forming electrode in said active matrix region, and

(b) said peripheral circuit comprising;

at least one CMOS circuit comprising a pair of an N-channel thin film transistor and a P-channel thin film transistor on said insulating surface of said substrate.

18. A semiconductor device comprising at least an active matrix region and a peripheral circuit,

(a) said active matrix region comprising:

a semiconductor island on an insulating surface of a substrate, said semiconductor island comprising at least first and second channel regions, and a plurality of impurity regions;

a gate insulating film on said semiconductor island;

at least first and second gate electrodes over said first and second channel regions with said gate insulating film interposed therebetween, respectively;

a gate line connected to said first and second gate electrodes;

a capacitor forming electrode over a portion in said semiconductor island with said gate insulating film interposed therebetween; and

a pixel electrode connected with said semiconductor island,

wherein said gate line is parallel to said capacitor forming electrode in said active matrix region, and

(b) said peripheral circuit comprising;

at least one CMOS circuit comprising a pair of an N-channel thin film transistor and a P-channel thin film transistor on said insulating surface of said substrate.

19. A semiconductor device comprising at least an active matrix region and a peripheral circuit,

(a) said active matrix region comprising:

a semiconductor island on an insulating surface of a substrate, said semiconductor island comprising at least first and second channel regions, and a plurality of impurity regions;

a gate insulating film adjacent to said semiconductor island;

at least first and second gate electrodes adjacent to said first and second channel regions with said gate insulating film interposed therebetween, respectively;

a capacitor forming electrode adjacent to a portion in said semiconductor island with said gate insulating film interposed therebetween;

a source line connected to said semiconductor island; and

a pixel electrode connected with said semiconductor island,

wherein said source line and said capacitor forming electrode cross at right angles in said active matrix region, and

(b) said peripheral circuit comprising;

at least one CMOS circuit comprising a pair of an N-channel thin film transistor and a P-channel thin film transistor on said insulating surface of said substrate.

20. A semiconductor device comprising at least an active matrix region and a peripheral circuit,

(a) said active matrix region comprising:

a semiconductor island on an insulating surface of a substrate, said semiconductor island comprising at least first and second channel regions, and a plurality of impurity regions;

a gate insulating film on said semiconductor island;

at least first and second gate electrodes over said first and second channel regions with said gate insulating film interposed therebetween, respectively;

a capacitor forming electrode over a portion in said semiconductor island with said gate insulating film interposed therebetween;

a source line connected to said semiconductor island; and

a pixel electrode connected with said semiconductor island,

wherein said source line and said capacitor forming electrode cross at right angles in said active matrix region, and

(b) said peripheral circuit comprising;

at least one CMOS circuit comprising a pair of an N-channel thin film transistor and a P-channel thin film transistor on said insulating surface of said substrate.

21. A semiconductor device comprising at least an active matrix region and a peripheral circuit,

(a) said active matrix region comprising:

a gate line connected to at least first and second gate electrodes formed over a substrate;

a signal line formed over said substrate;

a pixel electrode formed over said substrate;

a semiconductor island formed over said substrate, said semiconductor island having at least;

first and second channel regions adjacent to said first and said second gate electrodes, respectively,

a first impurity region located adjacent to said first channel forming region and connected to said signal line,

a second impurity region located between said first and second channel regions, and

a third impurity region located adjacent to second channel region,

wherein said first, second, and third impurity regions have a same conductivity type impurity; and

a capacitor forming electrode adjacent to a portion in said semiconductor island,

wherein said portion in the semiconductor island is a same conductivity type as said first and second channel regions, and

(b) said peripheral circuit comprising;

at least one CMOS circuit comprising a pair of an N-channel thin film transistor and a P-channel thin film transistor over said substrate, each of said an N-channel thin film transistor and a P-channel thin film transistor comprising;

a semiconductor island over said substrate, said semiconductor island having a channel region, and source and drain regions;

a gate insulating film adjacent to said semiconductor island; and

a gate electrode adjacent to said semiconductor island with said gate insulating film interposed therebetween,

wherein said semiconductor island of at least said N-channel thin transistor comprises a pair of LDD regions located between said channel region and said source and drain regions, respectively.

22. A semiconductor device comprising at least an active matrix region and a peripheral circuit,

(a) said active matrix region comprising:

a gate line connected to at least first and second gate electrodes formed over a substrate;

a signal line formed over said substrate;

a pixel electrode formed over said substrate;

a semiconductor island formed over said substrate, said semiconductor island having at least;

first and second channel regions under said first and said second gate electrodes, respectively,

a first impurity region located adjacent to said first channel forming region and connected to said signal line,

a second impurity region located between said first and second channel regions, and

a third impurity region located adjacent to second channel region,

wherein said first, second, and third impurity regions have a same conductivity type impurity; and

a capacitor forming electrode over a portion in said semiconductor island,

wherein said portion in the semiconductor island is a same conductivity type as said first and second channel regions, and

(b) said peripheral circuit comprising;

at least one CMOS circuit comprising a pair of an N-channel thin film transistor and a P-channel thin film transistor on said insulating surface of said substrate, each of said an N-channel thin film transistor and a P-channel thin film transistor comprising;

a semiconductor island over said substrate, said semiconductor island having a channel region, and source and drain regions;

a gate insulating film on said semiconductor island; and

a gate electrode over said semiconductor island with said gate insulating film interposed therebetween,

wherein said semiconductor island of at least said N-channel thin transistor comprises a pair of LDD regions between said channel region and said source and drain regions, respectively.

23. A semiconductor device comprising at least an active matrix region and a peripheral circuit,

(a) said active matrix region comprising:

a gate line connected to at least first and second gate electrodes formed over a substrate;

a signal line formed over said substrate;

a pixel electrode formed over said substrate;

a semiconductor island formed over said substrate, said semiconductor island having at least;

first and second channel regions adjacent to said first and said second gate electrodes, respectively,

a first impurity region located adjacent to said first channel forming region and connected to said signal line,

a second impurity region located between said first and second channel regions, and

a third impurity region located adjacent to second channel region,

wherein said first, second, and third impurity regions have a same conductivity type impurity; and

a capacitor forming electrode adjacent to a portion in said semiconductor island,

wherein said portion in the semiconductor island is a same conductivity type as said first and second channel regions, and

wherein said pixel electrode is in contact with said third impurity region, said third impurity region located between said second channel region and said portion in said semiconductor island, and

(b) said peripheral circuit comprising;

at least one CMOS circuit comprising a pair of an N-channel thin film transistor and a P-channel thin film transistor over said substrate.

24. A semiconductor device comprising at least an active matrix region and a peripheral circuit,

(a) said active matrix region comprising:

a gate line connected to at least first and second gate electrodes formed over a substrate;

a signal line formed over said substrate;

a pixel electrode formed over said substrate;

a semiconductor island formed over said substrate, said semiconductor island having at least;

first and second channel regions under said first and said second gate electrodes, respectively,

a first impurity region located adjacent to said first channel forming region and connected to said signal line,

a second impurity region located between said first and second channel regions, and

a third impurity region located adjacent to second channel region,

wherein said first, second, and third impurity regions have a same conductivity type impurity; and

a capacitor forming electrode over a portion in said semiconductor island,

wherein said portion in the semiconductor island is a same conductivity type as said first and second channel regions, and

wherein said pixel electrode is in contact with said third impurity region, said third impurity region located between said second channel region and said portion in said semiconductor island, and

(b) said peripheral circuit comprising;

at least one CMOS circuit comprising a pair of an N-channel thin film transistor and a P-channel thin film transistor over said substrate.

25. A semiconductor device comprising at least an active matrix region and a peripheral circuit,

(a) said active matrix region comprising:

a gate line connected to at least first and second gate electrodes formed over a substrate;

a signal line formed over said substrate;

a pixel electrode formed over said substrate;

a semiconductor island formed over said substrate, said semiconductor island having at least;

first and second channel regions adjacent to said first and said second gate electrodes, respectively,

a first impurity region located adjacent to said first channel forming region and connected to said signal line,

a second impurity region located between said first and second channel regions,

a third impurity region located adjacent to second channel region, and

a fourth impurity region located at one of ends of said semiconductor island,

wherein said first, second, third, and fourth impurity regions have a same conductivity type impurity; and

a capacitor forming electrode adjacent to a portion in said semiconductor island, said portion are a same conductivity type as said first and second channel regions,

wherein said portion is interposed between said third and fourth impurity regions, and

(b) said peripheral circuit comprising;

at least one CMOS circuit comprising a pair of an N-channel thin film transistor and a P-channel thin film transistor over said substrate.

26. A semiconductor device comprising at least an active matrix region and a peripheral circuit,

(a) said active matrix region comprising:

a gate line connected to at least first and second gate electrodes formed over a substrate;

a signal line formed over said substrate;

a pixel electrode formed over said substrate;

a semiconductor island formed over said substrate, said semiconductor island having at least;

first and second channel regions under said first and said second gate electrodes, respectively,

a first impurity region located adjacent to said first channel forming region and connected to said signal line,

a second impurity region located between said first and second channel regions,

a third impurity region located adjacent to second channel region, and

a fourth impurity region located at one of ends of said semiconductor island,

wherein said first, second, third, and fourth impurity regions have a same conductivity type impurity; and

a capacitor forming electrode over a portion in said semiconductor island, wherein said portion of said semiconductor island is a same conductivity type as said first and second channel regions,

wherein said portion is interposed between said third and fourth impurity regions, and

(b) said peripheral circuit comprising;

at least one CMOS circuit comprising a pair of an N-channel thin film transistor and a P-channel thin film transistor over said substrate.

27. A semiconductor device comprising at least an active matrix region and a peripheral circuit,

(a) said active matrix region comprising:

a gate line connected to at least first and second gate electrodes formed over a substrate;

a signal line formed over said substrate;

a pixel electrode formed over said substrate;

a semiconductor island formed over said substrate, said semiconductor island having at least;

first and second channel regions adjacent to said first and said second gate electrodes, respectively,

a first impurity region located adjacent to said first channel forming region and connected to said signal line,

a second impurity region located between said first and second channel regions, and

a third impurity region located adjacent to second channel region,

wherein said first, second, and third impurity regions have a same conductivity type impurity; and

a capacitor forming electrode adjacent to a portion in said semiconductor island,

wherein said portion in said semiconductor island is a same conductivity type as said first and second channel regions, and

wherein said gate line is parallel to said capacitor forming electrode in said active matrix region, and

(b) said peripheral circuit comprising;

at least one CMOS circuit comprising a pair of an N-channel thin film transistor and a P-channel thin film transistor over said substrate.

28. A semiconductor device comprising at least an active matrix region and a peripheral circuit,

(a) said active matrix region comprising:

a gate line connected to at least first and second gate electrodes formed over a substrate;

a signal line formed over said substrate;

a pixel electrode formed over said substrate;

a semiconductor island formed over said substrate, said semiconductor island having at least;

first and second channel regions under said first and said second gate electrodes, respectively,

a first impurity region located adjacent to said first channel forming region and connected to said signal line,

a second impurity region located between said first and second channel regions, and

a third impurity region located adjacent to second channel region,

wherein said first, second, and third impurity regions have a same conductivity type impurity; and

a capacitor forming electrode over a portion in said semiconductor island,

wherein said portion in said semiconductor island is a same conductivity type as said first and second channel regions, and

wherein said gate line is parallel to said capacitor forming electrode in said active matrix region, and

(b) said peripheral circuit comprising;

at least one CMOS circuit comprising a pair of an N-channel thin film transistor and a P-channel thin film transistor over said substrate.

29. A semiconductor device comprising at least an active matrix region and a peripheral circuit,

(a) said active matrix region comprising:

a gate line connected to at least first and second gate electrodes formed over a substrate;

a signal line formed over said substrate;

a pixel electrode formed over said substrate;

a semiconductor island formed over said substrate, said semiconductor island having at least;

first and second channel regions adjacent to said first and said second gate electrodes, respectively,

a first impurity region located adjacent to said first channel forming region and connected to said signal line,

a second impurity region located between said first and second channel regions, and

a third impurity region located adjacent to second channel region,

wherein said first, second, and third impurity regions have a same conductivity type impurity; and

a capacitor forming electrode adjacent to a portion in said semiconductor island,

wherein said portion in said semiconductor island a same conductivity type as said first and second channel regions,

wherein said source line and said capacitor forming electrode cross at right angles in said active matrix region, and

(b) said peripheral circuit comprising;

at least one CMOS circuit comprising a pair of an N-channel thin film transistor and a P-channel thin film transistor over said substrate.

30. A semiconductor device comprising at least an active matrix region and a peripheral circuit,

(a) said active matrix region comprising:

a gate line connected to at least first and second gate electrodes formed over a substrate;

a signal line formed over said substrate;

a pixel electrode formed over said substrate;

a semiconductor island formed over said substrate, said semiconductor island having at least;

first and second channel region under said first and said second gate electrodes, respectively,

a first impurity region located adjacent to said first channel forming region and connected to said signal line,

a second impurity region located between said first and second channel regions, and

a third impurity region located adjacent to second channel region,

wherein said first, second, and third impurity regions have a same conductivity type impurity; and

a capacitor forming electrode over a portion in said semiconductor island,

wherein said portion in said semiconductor island a same conductivity type as said first and second channel regions,

wherein said source line and said capacitor forming electrode cross at right angles in said active matrix region, and

(b) said peripheral circuit comprising;

at least one CMOS circuit comprising a pair of an N-channel thin film transistor and a P-channel thin film transistor over said substrate.