Low voltage active body semiconductor device

• US 5,998,847 A
• Filed: 08/11/1998
• Issued: 12/07/1999
• Est. Priority Date: 08/11/1998
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Bertin, Claude L., Mandelman, Jack Allan, Gambino, Jeffrey P., Hsu, Louis Lu-Chen, Assaderaghi, Fariborz
• Primary Examiner(s): Monin, Jr., Donald L.
• Assistant Examiner(s): DIETRICH, MICHAEL C
• Application Number:
  US09/132,599
• Time in Patent Office: 483 Days
• Field of Search: 257/192, 257/217, 257/377, 257/387, 257/391, 257/413, 257/508, 257/900, 257/392, 257/393, 257/394, 257/403, 257/401
• US Class Current: 257/401
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78615 with a body contact
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

An active FET body device which comprises an active FET region including a gate, a body region and electrical connection between said gate and said body region that is located within the active FET region is provided along with various methods for fabricating the devices. The electrical connection extends over substantially the entire width of the FET.

Claims

1. An active FET body device which comprises an active FET region including a gate;

a channel region and electrical connection between said gate and said channel region located within said active FET region, wherein the electrical connection extends over substantially the entire width of the FET.

2. The active FET body device of claim 1 comprising a SOI substrate.

3. The device of claim 1 wherein said connection between said gate and said channel region is self-aligned to edges of the gate.

4. The device of claim 2 being a SOI DRAM array device, logic device or driver device.

5. The active FET body device of claim 1 wherein a metallic silicide and silicon oxide structure are located on top of said gate to act as a cap for said gate.

6. The active FET body device according to claim 1 wherein said gate is doped polysilicon.

7. The active FET body device of claim 1 wherein the length of the electrical connection between the gate and channel region along a surface of the FET is about 200 Å

or less.

8. The active FET body device of claim 1 wherein the length of the electrical connection between the gate and channel region along a surface of the FET is about 100 Å

or less.