Phase compensating apparatus and delay controlling circuit

• US 5,999,027 A
• Filed: 05/28/1996
• Issued: 12/07/1999
• Est. Priority Date: 06/13/1995
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Yamazaki, Hiroshi
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Adolphe, Eunja
• Application Number:
  US08/654,975
• Time in Patent Office: 1,288 Days
• Field of Search: 327/149, 327/150-153, 327/158, 327/159, 327/161, 327/146, 327/155, 327/233-236, 327/243-245, 327/250, 327/251, 327/261, 327/263, 327/276, 327/292
• US Class Current: 327/161
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled

Abstract

A delay/digital converting circuit in a phase compensating apparatus detects a time period after a measurement start signal that is an internal clock signal is input, until a measurement end signal that is an output signal of a digital/delay converting circuit is input, and outputs the resultant data as digital data to a digital/delay converting circuit. The delay/digital converting circuit outputs the difference between the cycle of an external clock signal and an amount of delay time of a clock distributing circuit as the digital data. The digital/delay converting circuit delays the external clock signal according to the digital data. An internal clock signal which is the output signal of the digital/delay converting circuit that has been delayed by the clock distributing circuit is a signal that has a delay for one cycle of the external clock signal. Thus, the phase of the external clock signal accords with the phase of the internal clock signal.

Claims

1. A phase compensating apparatus comprising:

phase difference compensation signal outputting means for outputting a signal, obtained by delaying an external clock signal based on digital delay time data, for compensating for a phase difference between the external clock signal and an internal clock signal;

a structural element for receiving the signal outputted from said phase difference compensation signal outputting means and outputting the internal clock signal; and

delay time detecting means for receiving the signal outputted from the phase difference compensation signal outputting means and the internal clock signal and detecting a difference between a delay caused by the structual element and a cycle of the external clock signal based on the received signals, and outputting the detected difference as digital delay time data to said phase difference compensation signal outputting means.

2. The phase compensating apparatus as set forth in claim 1, wherein a delay added by said phase difference compensation signal outputting means makes a total of the delay and the delay caused by the structural element equal to an integer multiple of the cycle of the external clock signal, whereby the phase of the internal clock signal accord with the phase of the external clock signal.

3. A phase compensating apparatus comprising:

delay time detecting means for subtracting a delay time period of an internal signal having a delay, with respect to an input signal, from the cycle of the input signal and outputting the result as digital delay time data;

phase difference compensation signal outputting means for delaying the input signal corresponding to the digital delay time data so as to compensate for the phase difference between the input signal and the internal signal to produce a first output signal;

delaying means for delaying the first output signal corresponding to a setting value which becomes a desired delay to produce a second output signal; and

waveform generating means for generating a resultant signal corresponding to the first output signal and the second output signal and outputting the resultant signal.

4. The phase compensating apparatus as set forth in claim 3,

wherein said waveform generating means generates and outputs the resultant signal whose signal level becomes "H" as the signal level of the first output signal becomes "H", and whose signal level becomes "L" as the signal level of the second output signal becomes "H".

5. The phase compensating apparatus as set forth in claim 3,

wherein the resultant signal causes the phase of the internal signal to be the same as the phase of the input signal and causes a waveform of the internal signal to have a desired duty ratio corresponding to the setting value.

6. A phase compensating apparatus comprising:

first delay/digital converting means for outputting digital delay time data having a value corresponding to a time period measured from when a signal level of a second signal, having a delay with respect to a first signal, becomes "H" or "L" until a signal level of the first signal becomes "H" or "L";

first digital/delay converting means for outputting the first signal corresponding to an input signal delayed according to the digital delay time data;

a cycle detecting circuit for detecting the cycle of the input signal;

a calculating circuit for calculating an "H" level period or "L" level period of a signal that has a cycle detected by said cycle detecting circuit and that has a desired duty ratio;

second digital/delay converting means for outputting a third signal corresponding to the first signal delayed for a time period corresponding to the "H" or "L" level calculated by said calculating circuit; and

a waveform generating circuit for generating a signal whose signal level varies as the signal level of the first signal or the signal level of the third signal becomes "H" or "L".

7. The phase compensating apparatus as set forth in claim 6,

wherein said calculating circuit performs one of shifting each bit of the third signal by one bit, and shifting each bit of the input signal by 2 bits.

8. The phase compensating apparatus as set forth in claim 6, further comprising:

a clock distributing circuit for distributing an output signal of said waveform generating circuit as an internal clock signal and for outputting a portion of the internal clock signal to said first digital/delay converting means as the second signal,

wherein said first delay/digital converting means outputs digital delay time data based on a delay amount of the first signal corresponding to the internal clock signal, and

said first digital/delay converting means outputs, as the first signal, a signal corresponding to an external clock signal supplied as the input signal delayed based on the digital delay time data so that the phase of the external clock signal accords with the phase of the internal clock signal.

9. The phase compensating apparatus as set forth in claim 6,

wherein said cycle detecting circuit has a second delay/digital converting means for outputting a period of one cycle of the input signal as a second digital delay time data.

10. A phase compensating apparatus comprising:

first delay/digital converting means for outputting digital delay time data having a value corresponding to a time period measured from when a signal level of a second signal, having a delay with respect to a first signal, becomes "H" or "L" until a signal level of the first signal becomes "H" or "L";

first digital/delay converting means for outputting the first signal corresponding to an input signal delayed according to the digital delay time data;

a cycle detecting circuit for detecting the cycle of the input signal;

a first calculating circuit for calculating a delay amount for the first signal;

second digital/delay converting means for delaying the first signal based on the delay amount calculated by said first calculating circuit;

a second calculating circuit for calculating an "H" level period or an "L" level period of a signal that has a cycle detected by said cycle detecting circuit and that has a desired duty ratio;

an OR circuit for ORing output from said first signal digital/delay converting means and an output signal of said second digital/delay converting circuit;

third digital/delay converting means for delaying an output signal of said OR circuit based on the "H" or "L" level period; and

a waveform generating circuit for generating a signal whose signal level varies as the signal levels of the output signals of said OR circuit and said third digital/delay converting means becomes "H" or "L".

11. The phase compensating apparatus as set forth in claim 10, further comprising:

fourth digital/delay converting means for delaying an output signal of said second digital/delay converting means based on the delay amount calculated by said first calculating circuit,

wherein said OR circuit ORs the output signals of said first digital/converting means, said second digital/converting means, and said fourth digital/converting means.

12. The phase compensating apparatus as set forth in claim 11,

wherein said waveform generating circuit is adapted for generating a signal whose signal level becomes "H" as the signal level of the output signal of said OR circuit becomes "H", and whose signal level becomes "L" as the signal level of the output signal of said third or fourth digital/delay converting means becomes "H".

13. A phase compensating apparatus comprising:

first delay/digital converting means for outputting digital delay time data having a value corresponding to a time period measured from when a signal level of a second signal, having a delay with respect to a first signal, becomes "H" or "L" until a signal level of the first signal becomes "H" or "L";

first digital/delay converting means for outputting the first signal corresponding to an input signal delayed according to the digital delay time data;

a cycle detecting circuit for detecting the cycle of the input signal;

a first calculating circuit for calculating a delay amount for the first signal;

second digital/delay converting means for delaying the first signal by the calculated delay amount for the first signal;

a second calculating circuit for calculating an "H" level period or "L" level period of a signal that has a cycle detected by said cycle detecting circuit and that has a desired duty ratio;

third digital/delay converting means for delaying an output signal of said second digital/delay converting means by the "H" or "L" level period; and

a waveform generating circuit for generating a signal whose signal level varies as the signal levels of output signals of said second digital/delay converting means and said third digital/delay converting means becomes "H" or "L".

14. The phase compensating apparatus as set forth in claim 13, further comprising:

a clock distributing circuit for distributing the output signal of said waveform generating circuit as an internal clock signal,

wherein said second digital/delay converting means delays the first signal by the delay amount calculated by said first calculating circuit and causes said clock distributing circuit to output the internal clock signal with a predetermined phase difference against the input signal.

15. The phase compensating apparatus as set forth in claim 13,

wherein said waveform generating circuit generates a signal whose signal level becomes "H" as the signal level of the output signal of said second digital/delay converting means becomes "H", and whose signal level becomes "L" as the signal level of the output of said third digital/delay converting means becomes "H".

16. The phase compensating apparatus as set forth in claim 13,

wherein said first calculating circuit designates an amount of delay for shifting the phase of an internal clock signal from the phase of an external clock signal supplied as the input signal.

17. A delay controlling circuit, comprising:

delay/digital converting means for outputting digital delay time data indicating a delay by a structural element in a subsequent stage between a measurement start signal and a measurement end signal; and

digital/delay converting means for delaying an input signal based on the digital delay time data to produce a resultant signal, and outputting the resultant signal to the structural element in the subsequent stage.

18. The delay controlling circuit as set forth in claim 17,

wherein the input signal is an external clock signal,

the measurement end signal is a signal which is the external clock signal that has been delayed for the digital delay time data, and

the measurement start signal is an internal clock signal that has a delay from the measurement end signal.

19. A delay controlling circuit, comprising:

a delay/digital converting circuit for outputting delay time data corresponding to a delay by a structural element in a subsequent stage between a measurement start signal and a measurement end signal;

calculating means for performing a predetermined calculation on the delay time data; and

digital/delay converting means for outputting to the structural element in the subsequent stage a signal based on the input signal delayed by an amount indicated by said calculating means.

20. The delay controlling circuit as set forth in claim 19,

wherein the input signal is an external clock signal,

the measurement end signal is a signal corresponding to an external clock signal delayed based on the delay time data, and

the measurement start signal is an internal clock signal having a delay with respect to the measurement end signal.

21. A phase compensating apparatus comprising:

a phase difference compensation signal outputting circuit for outputting a signal, obtained by delaying an external clock signal based on digital delay time data, for compensating for a phase difference between the external clock signal and an internal clock signal;

a structural element for receiving the signal outputted from said phase difference compensation signal outputting circuit and outputting the internal clock signal; and

a delay time detecting circuit for receiving the signal outputted from said phase difference compensation signal outputting circuit and the internal clock signal and detecting a difference between a delay caused by the internal structural element and a cycle of the external clock signal based on the received signals, and outputting the detected difference as the digital delay time data to said phase difference compensation outputting circuit.

22. A phase compensating apparatus for compensating for a phase difference between an input signal having a cycle and an internal signal, the phase compensating apparatus comprising:

a first delay/digital converting circuit for subtracting a delay time period introduced by a structural element in a subsequent stage between the input signal and a second signal from the cycle of the input signal to produce digital delay time data; and

a first digital/delay converting circuit for delaying the input signal based on the digital delay time data and outputting a resultant signal to the structural element in the subsequent stage.

23. A phase compensating method for compensating for a phase difference between an input signal having a cycle and an internal signal, the method comprising the steps of:

subtracting a delay time period introduced by a structural element in a subsequent stage between the internal signal and the input signal, from a cycle of the input signal to produce digital delay time data; and

delaying the input signal based on the digital delay time data to compensate for a phase difference between the input signal and the internal signal and outputting the delayed input signal to the structural element in the subsequent stage.

24. A phase compensating method, comprising the steps of:

outputting a value corresponding to a time period introduced by a structural element in a subsequent stage after a signal level of a second signal becomes "H" or "L" until the signal level of a first signal becomes "H" or "L" as digital delay time data; and

outputting a signal which is an input signal that has been delayed according to the digital delay time as the first signal to the structural element in the subsequent stage.

25. A delay controlling method, comprising the steps of:

outputting a delay introduced by a structural element in a subsequent stage between a measurement start signal and a measurement end signal as digital delay time data; and

delaying an input signal for the digital delay time data and outputting a resultant signal to the structural element in the subsequent stage.