Digital frequency synthesizer system and method

• US 5,999,060 A
• Filed: 11/30/1998
• Issued: 12/07/1999
• Est. Priority Date: 03/30/1998
• Status: Expired due to Fees

• Current Assignee: Pll Dynamics Limited
• Original Assignee: Pll Dynamics Limited
• Inventors: Zuta, Marc
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US09/201,165
• Time in Patent Office: 372 Days
• Field of Search: 331/1 A, 331/14, 331/16, 331/25
• US Class Current: 331/14
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/181 a numerical count result being used for locking the loop, the counter counting during fixed time intervals H03L7/1806 takes precedence
• CPC Class Codes: H03L 7/187 using means for coarse tuning the voltage controlled oscillator of the loop H03L7/191 - H03L7/195 take precedence
• CPC Class Codes: H03L 7/191 using at least two different signals from the frequency divider or the counter for determining the time difference H03L7/193, H03L7/195 take precedence
• CPC Class Codes: H03L 7/199 with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation

Abstract

A frequency synthesizer includes a first counter for counting cycles of an input clock and for generating a reference output bus, a VCO for generating an output signal, a second counter for counting cycles of the output signal and for generating a VCO output bus, and a phase detector for measuring the phase error between the reference bus and the VCO output bus and for generating a control signal which is applied to the control input of the VCO. The phase detector includes circuitry for computing a corrected bus by multiplying the VCO output bus with a correction coefficient proportional to the reciprocal of the modulo count of the second counter.

Claims

1. A frequency synthesizer for generating a signal at a desired frequency, comprising:

A. a voltage controlled oscillator (VCO) for generating an output signal at a frequency responsive to a signal at its control input;

B. a first means for counting cycles of a reference input clock and for generating a first output bus accordingly, and a second means for counting cycles of the output signal and for generating a second output bus accordingly, wherein the modulo count of each of the counting means is set to values corresponding to the desired frequency and a desired frequency step, and wherein a correction is applied to at least one of the output buses so as to bring the two output buses to the same counting range;

C. phase detector means for measuring a phase error using several bits from the first output bus and the second output bus, for generating a control signal derived from the phase error value and for applying the control signal to the control input of the VCO to close a phase control loop.

2. The frequency synthesizer according to claim 1, further including low pass filter means between said phase detector and said VCO control input.

3. The frequency synthesizer according to claim 1, further including digital to analog converter means after the phase detector, and wherein said VCO accepts a control input in analog form.

4. The frequency synthesizer according to claim 2, wherein said low pass filter has a cutoff frequency lower than the rate of update of said phase error.

5. The frequency synthesizer according to claim 1, further including control means for accepting a digital command indicative of the desired output frequency, and for setting said modulo count and for applying said bus correction according to said frequency.

6. The frequency synthesizer according to claim 1, further including means for resetting said first counter means and said second counter means when a digital command indicative of a request for a change of frequency is received.

7. The frequency synthesizer according to claim 1, further including control means to perform separate, alternating cycles of first, phase error measurement and second, VCO correction.

8. The frequency synthesizer according to claim 1, further including control means to the VCO which takes into account the modulo count error because of the VCO counter and for limiting the maximal VCO frequency deviation, to perform a controlled phase correction.

9. The frequency synthesizer according to claim 1, further including means for synchronizing the VCO correction with system operation constraints.

10. The frequency synthesizer according to claim 1, further including analog phase detector means, wherein one of said counters further includes means for generating a signal corresponding to the quadrature of the most significant bit, and said analog phase detector measures the phase difference between said signal in quadrature derived from one counter and the most significant bit of the other counter.

11. A method for generating a synthesized frequency signal, comprising the steps of:

A. counting cycles of a fixed frequency clock signal, to generate a reference bus which contains a digital representation of the counting result at any given time, wherein the time for a full count is the reciprocal of the reference frequency;

B. counting cycles of a Voltage Controlled Oscillator (VCO), to generate a VCO bus which contains a digital representation of the counting result, and wherein the modulo of the VCO count determines the output frequency of the VCO, with the frequency being the result of multiplication of the reference frequency and the modulo count of the VCO;

C. correcting the VCO bus by multiplying with a digital coefficient which is proportional to the reciprocal of the modulo count of the VCO;

D. computing a phase error by subtracting the corrected VCO bus derived in step (C) from the reference bus derived in step (A); and

E. generating a correction signal proportional to the phase error found in step (D), and applying the correction signal to the control input of the VCO, to correct its frequency accordingly.

12. A method for generating a synthesized frequency signal, comprising the steps of:

A. counting cycles of a fixed frequency clock signal, to generate a reference bus which contains a digital representation of the counting result at any given time, wherein the time for a full count is the reciprocal of the reference frequency;

B. counting cycles of a Voltage Controlled Oscillator (VCO), to generate a VCO bus which contains a digital representation of the counting result, and wherein the modulo of the VCO count determines the output frequency of the VCO, with the frequency being the result of multiplication of the reference frequency and the modulo count of the VCO;

C. correcting the reference bus by multiplying with a digital coefficient which is proportional to the modulo count of the VCO;

D. computing a phase error by subtracting the corrected reference bus derived in step (C) from the VCO bus derived in step (B); and

E. generating a correction signal proportional to the phase error found in step (D), and applying the correction signal to the control input of the VCO, to correct its frequency accordingly.