Synchronized data processing system and image processing system

• US 5,999,197 A
• Filed: 09/30/1997
• Issued: 12/07/1999
• Est. Priority Date: 10/15/1993
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd.
• Inventors: Miyamoto, Takashi, Satoh, Jun, Yamagishi, Kazushige, Watabe, Mitsuru, Nakashima, Keisuke, Ohmura, Kenichiroh, Katsura, Koyo
• Primary Examiner(s): Tung, Kee M.
• Application Number:
  US08/940,632
• Time in Patent Office: 798 Days
• Field of Search: 345/515, 345/516, 345/501, 345/507-509, 345/502, 345/514, 711/5, 711/1, 711/158, 711/147, 711/218, 395/556, 395/553, 713/500, 713/400
• US Class Current: 345/567
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 15/7832 on one IC chip (single chip microprocessors)
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G09G 2320/0252 Improving the response speed
• CPC Class Codes: G09G 2350/00 Solving problems of bandwidth in display systems
• CPC Class Codes: G09G 2360/128 Frame memory using a Synchronous Dynamic RAM [SDRAM]
• CPC Class Codes: G09G 2370/10 Use of a protocol of communication by packets in interfaces along the display data pipeline
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory
• CPC Class Codes: G09G 5/395 Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen G09G5/399 takes precedence
• CPC Class Codes: G09G 5/399 using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers
• CPC Class Codes: G11C 8/04 using a sequential addressing device, e.g. shift register, counter
• CPC Class Codes: G11C 8/06 Address interface arrangements, e.g. address buffers
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.

Claims

1. A data processing system comprising:

a rewritable memory, including an address counter and a mode register adapted to input an address, input and output data and input a control signal in synchronism with a clock signal and to update the address, which is preset in said address counter, at times in number corresponding to the set number of said mode register, to read and write the data sequentially; and

a data processor which provides data and addresses to access said memory and for utilizing said memory in at least a frame buffer to process image data, wherein said data processor includes means for issuing a value to be set into said mode register and a command to set said value into said mode register in accordance with the condition at the data processing.

2. A data processing system according to claim 1, further comprising:

an input terminal for receiving an external signal to regulate the timing for issuing said command.

3. A data processing system according to claim 1,

wherein said data processor further includes;

instruction control means for executing an instruction which is allocated to the issue of the command.

4. A data processing system according to claim 1,

wherein said data processor further includes:

an address decoder for detecting an internal access to an address which is allocated to the issue of the command; and

a sequencer for issuing said command in accordance with the result of detection by said address decoder and for outputting the data to be subjected to said internal access, as the value to the outside.

5. A data processing system comprising:

a memory; and

a data processor for accessing said memory in processing image data,

wherein said memory includes a plurality of memory banks and an address counter, and is enabled to input an address, input and output data and input a control signal in synchronism with a clock signal, wherein said memory has a burst mode, in which said memory is accessed while updating an address preset in said address counter, so that said memory can receive an address active command for setting the access address in another memory bank in parallel with the operation of a memory bank being operated in the burst mode, and

wherein said data processor includes;

data processing modules for producing data and addresses to access said memory and for processing the image data by using said memory in at least a frame buffer; and

bus control means for issuing said active address command in response to the instruction of an access from said data processing module for a memory bank different from the memory bank being accessed in the burst mode, to enable the access address to be set in advance.

6. A data processing system comprising:

first and second memories for latching a row address to enable the same row address as the once latched one to be sequentially accessed by updating a column address, and for inputting an address, inputting and outputting data and inputting a control signal in synchronism with a clock signal;

memory buses allocated to said first and second memories, respectively;

bus control means allocated to said memory buses, respectively;

a data processing module coupled to said bus control means for producing data and addresses to access said first and second memories thereby to process the data read out from said first memory, and for producing the access addresses in parallel for said first and second memories to store the results of the data processing in said second memory; and

delay means for transmitting the address for said second memory, which is outputted from said data processing module, to said second memory with a delay time period corresponding to that for said data processing.

7. A data processing system according to claim 6, further comprising:

mishit means for detecting at substantially the same timing whether or not the row addresses of the individual access addresses outputted in parallel from said data processing module to said first and second memories are coincident to the preceding row address fed; and

means for interrupting the operation of said data processing module, while the row address of said mishit is being updated, when the incoincidence of said row address is detected by said mishit detecting means.

8. A data processing system comprising:

first and second memories for latching row addresses to enable the same row address as one once latched to be sequentially accessed by updating a column address, and for inputting an address, inputting and outputting data and inputting a control signal in synchronism with a clock signal;

first and second memory buses allocated to said first and second memories, respectively;

first and second bus control means allocated to said first and second memory buses, respectively;

a data processing module coupled to said first and second bus control means for producing data and addresses to access said first and second memories thereby to process the data read out from said first memory and for producing and outputting the access addresses to said first and second memories in parallel to store the result of the data processing in said second memory;

delay means for transmitting the access address for said second memory, which is outputted from said data processing module, to said second memory with a delay time period corresponding to the time period for said data processing;

first mishit detecting means for detecting whether or not the row address outputted from said data processing module toward said first memory is coincident to the preceding row address fed;

second mishit detecting means for detecting whether or not the row address outputted from said data processing module toward said second memory is coincident to the preceding row address fed, such that its detection timing is made substantially concurrent with that by said first mishit detecting means; and

means for interrupting the operation of said data processing module while the row address relating to said mishit is being updated, when either said first or second mishit detecting means detects the incoincidence.

9. A data processing system comprising:

a memory for latching a row address to enable the same address as the once latched one to be sequentially accessed by updating a column address and for inputting an address, inputting and outputting data and inputting a control signal in synchronism with a clock signal;

a plurality of data processing modules for producing data and addresses to access said memory;

mishit detecting means for detecting whether or not the row address outputted from said data processing modules toward said memory is coincident to the preceding row address fed;

detecting means for detecting a change in the data processing modules to access said memory; and

bus control means for instructing said memory to update the row address for said access in response to either the detection of the incoincidence by said mishit detecting means or the detection of the change in the access subject by said detecting means.

10. A data processing system comprising:

a rewritable memory having a burst write mode and a mode register, number data in the mode register specifying a burst length in the burst write mode so that data in a number corresponding to the number data is written sequentially; and

a data processor for accessing the rewritable memory as a frame buffer to draw image data into the rewritable memory, wherein the data processor includes means for generating number data to be set in the mode register in accordance with a drawing condition so that the number data is made to a value 1 when memory addresses of the rewritable memory to draw the image data are not continuous in the same row of the rewritable memory, and the number data is set to a value N (N>

1) when memory addresses of the rewritable memory to draw the image data are continuous in the same row of the rewritable memory.

11. A data processing system according to claim 10,

wherein the rewritable memory receives an address, data and a control signal in synchronism with a clock signal supplied thereto, and the rewritable memory includes an address counter, an address value in the address counter being updated by a time in accordance with the number corresponding to the number data set in the mode register during the burst write mode, and

wherein the data processor includes means for generating the data and the address to access the rewritable memory, and means for issuing a command for setting the number data into the mode register.

12. A data processing system according to claim 11,

wherein the data processor further comprises an input terminal for receiving an external signal to regulate the timing for issuing the command.

13. A data processing system according to claim 11,

wherein the data processor further includes instruction control means for executing an instruction which is allocated to the issue of the command.

14. A data processing system according to claim 13,

wherein said data processor further includes:

an address decoder for detecting an internal access to the address which is allocated to the issue of the command; and

a sequencer for issuing the command in accordance with the result of detection by said address decoder and for outputting the data to be subjected to said internal access, as the number data for the mode register to the outside thereof.

15. A data processing system according to claim 10,

wherein the rewritable memory is a synchronous random access memory.

16. A data processing system according to claim 10,

wherein the number data is set to the value 1 when the data processor processes a line drawing in an arbitrary direction, and wherein the number data is set to the value N (N>

1) when the data processor processes rectangular smearing drawing.