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Synchronized data processing system and image processing system

  • US 5,999,197 A
  • Filed: 09/30/1997
  • Issued: 12/07/1999
  • Est. Priority Date: 10/15/1993
  • Status: Expired due to Term
First Claim
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1. A data processing system comprising:

  • a rewritable memory, including an address counter and a mode register adapted to input an address, input and output data and input a control signal in synchronism with a clock signal and to update the address, which is preset in said address counter, at times in number corresponding to the set number of said mode register, to read and write the data sequentially; and

    a data processor which provides data and addresses to access said memory and for utilizing said memory in at least a frame buffer to process image data, wherein said data processor includes means for issuing a value to be set into said mode register and a command to set said value into said mode register in accordance with the condition at the data processing.

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