Graphics address remapping table entry feature flags for customizing the operation of memory pages associated with an accelerated graphics port device

• US 5,999,198 A
• Filed: 09/09/1997
• Issued: 12/07/1999
• Est. Priority Date: 05/09/1997
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Elliott, Robert C., Lester, Robert Allan, Jones, Phillip M., Santos, Gregory N., Horan, Ronald T.
• Primary Examiner(s): Tung, Kee M.
• Assistant Examiner(s): Luu, Sy D.
• Application Number:
  US08/925,772
• Time in Patent Office: 819 Days
• Field of Search: 345/503, 345/520-521, 345/514, 345/522, 345/526, 345/515, 345/516, 345/507, 345/509, 711/206-207, 395/306-309, 395/310, 710/126-129
• US Class Current: 345/531
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 3/14 Digital output to display device ; Cooperation and interconnection of the display device with other functional units
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a memory page, and feature flags that may be used to customize the associated memory page.

Claims

1. A computer system having a core logic chipset which connects a computer processor and memory to an accelerated graphics port (AGP), said system comprising:

a system processor executing software instructions and generating graphics data;

a system memory having an addressable memory space comprising a plurality of bytes of storage, wherein each of said plurality of bytes of storage has a unique address;

said software instructions and said graphics data being stored in some of said plurality of bytes of storage of said system memory, wherein said graphics data is stored in a plurality of pages of graphics data, each of said plurality of pages of graphics data comprising a number of said plurality of bytes of storage;

a core logic chipset comprising,

an accelerated graphics port (AGP) request queue;

an AGP reply queue;

an AGP data and control logic;

an AGP arbiter;

an AGP cache;

a memory interface and control logic connected to said system memory; and

a processor interface connected to said system processor;

wherein,

said AGP request and reply queues are connected to said memory interface and control logic;

said AGP data and control logic is connected to said memory and interface control logic;

said AGP data and control logic and said AGP arbiter are connected to an AGP bus having an AGP processor, wherein said AGP processor generates video display data from said graphics data for display on a video display; and

a graphics address remapping table (GART table) having a plurality of entries, each of said plurality of GART table entries comprising an address pointer to a corresponding one of said plurality of pages of graphics data and feature flags for customizing said corresponding one of said plurality of pages of graphics data, wherein said core logic chipset uses said plurality of GART table entries for remapping said plurality of pages of graphics data into an AGP device address space for use by said AGP processor in generating said video display data, and said feature flags for customizing the operation thereof.

2. The computer system of claim 1, further comprising said core logic having interface logic for connecting said system processor and said system memory to input-output devices on a peripheral component interconnect (PCI) bus.

3. The computer system of claim 2, further comprising said core logic having interface logic for connecting said AGP bus to said PCI bus.

4. The computer system of claim 1, wherein said system processor is a plurality of system processors.

5. The computer system of claim 1, wherein said plurality of pages of graphics data are stored in said system memory in a non-contiguous and random order.

6. The computer system of claim 1, wherein each of said plurality of GART table entries comprises a plurality of binary bits wherein a first number of most significant bits of said plurality of binary bits represents said address pointer which contains a base address of said corresponding one of said plurality of pages of graphics data.

7. The computer system of claim 6, wherein a second number of least significant bits of said plurality of binary bits comprise said feature flags for said corresponding one of said plurality of pages of graphics data.

8. The computer system of claim 1, wherein said plurality of GART table entries are stored in said system memory.

9. The computer system of claim 1, wherein said plurality of GART table entries are stored in a plurality of pages of GART table entries in said system memory.

10. The computer system of claim 9, wherein said plurality of pages of GART table entries are stored in said system memory in a non-contiguous and random order.

11. The computer system of claim 10, further comprising a GART directory having a plurality of entries, each of said plurality of GART directory entries comprising an address pointer to a corresponding one of said plurality of pages of GART table entries, wherein said core logic chipset uses said plurality of GART directory entries for locating said plurality of pages of GART table entries in said system memory.

12. The computer system of claim 1, wherein the number of said plurality of bytes of storage in each of said plurality of pages of graphics data is 4096 bytes.

13. The computer system of claim 1, wherein said core logic chipset is at least one integrated circuit.

14. The computer system of claim 13, wherein the at least one integrated circuit core logic chipset is at least one application specific integrated circuit.

15. The computer system of claim 13, wherein the at least one integrated circuit core logic chipset is at least one programmable logic array integrated circuit.

16. The computer system of claim 1, further comprising a video display.

17. The computer system of claim 1, further comprising a network interface card, a hard disk, a floppy disk drive, a modem, a keyboard, and a mouse.

18. The computer system of claim 1, further comprising a serial port, a parallel port, a keyboard and a real time clock.

19. The computer system of claim 1, further comprising a read only memory basic input-output system (ROM BIOS), a non-volatile random access memory (NVRAM), a tape drive and a CD ROM drive.

20. A core logic chipset adapted for connecting a computer processor and memory to an accelerated graphics port (AGP) bus, comprising:

an accelerated graphics port (AGP) request queue;

an AGP reply queue;

an AGP data and control logic;

an AGP arbiter;

an AGP cache;

a memory interface and control logic adapted for connection to a system memory; and

a processor interface adapted for connection to at least one processor, wherein,

said AGP request and reply queues are connected to said memory interface and control logic;

said AGP data and control logic is connected to said memory and interface control logic;

said AGP data and control logic and said AGP arbiter are adapted for connection to an AGP bus having an AGP device;

wherein,

said AGP data and control logic is adapted to use a graphics address remapping table (GART table) having a plurality of entries, each of the plurality of GART table entries comprises an address pointer to a corresponding one of a plurality of pages of graphics data in the system memory and feature flags for customizing the corresponding one of the plurality of pages of graphics data.

21. The core logic chipset of claim 20, further comprising:

the host interface adapted for connecting the at least one processor to a peripheral component interconnect (PCI) bus;

a PCI to PCI interface adapted for connecting the PCI bus to the AGP bus, wherein PCI transactions are transferred between the PCI bus and the AGP bus.