Addressable matrix array containing electrodes with a variety of resistances for ferroelectric liquid crystal device

• US 5,999,242 A
• Filed: 05/06/1997
• Issued: 12/07/1999
• Est. Priority Date: 05/17/1996
• Status: Expired due to Fees

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.), The secretary of state for defence in her Britannic Majesty's Government of the United Kingdom of Great Britain And Northern Ireland
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.), The secretary of state for defence in her Britannic Majesty's Government of the United Kingdom of Great Britain And Northern Ireland
• Inventors: Walton, Harry Garth, Towler, Michael John
• Primary Examiner(s): Sikes, William L.
• Assistant Examiner(s): Horney, Kari M.
• Application Number:
  US08/851,616
• Time in Patent Office: 945 Days
• Field of Search: 349/37, 349/72, 349/143, 349/148, 349/161, 345/97, 345/100
• US Class Current: 349/148
• CPC Class Codes: G02F 1/133382 Heating or cooling of liquid crystal cells other than for activation, e.g. circuits or arrangements for temperature control, stabilisation or uniform distribution over the cell
• CPC Class Codes: G02F 1/13439 characterised by their electrical, optical, physical properties; materials therefor; method of making

Abstract

An addressable matrix display comprises an addressable matrix of pixels, a first set of electrode tracks on one side of the matrix and a second set of electrode tracks on the other side of the matrix. The sets of electrode tracks cross one another at the locations of the pixels, and the pixels are switchable by the application of respective switching waveforms to the electrode tracks. Furthermore at least one of the electrode tracks has a resistance which varies along the length of the electrode track in order to provide increased temperature uniformity over the display due to power dissipation during switching by the switching waveforms applied to the electrode tracks. More particularly the resistance in an intermediate section of the electrode track is greater than the resistance in two end sections of the electrode track.

Claims

1. An addressable matrix array comprising an addressable matrix of switching elements, a first set of electrode tracks on one side of the matrix, and a second set of electrode tracks on the other side of the matrix, the first and second sets of electrode tracks crossing one another at the locations of the switching elements and the switching elements being switchable by the application of respective switching waveforms to the first and second sets of electrode tracks, and at least one of the electrode tracks having a resistance which varies along the length of the electrode track in order to provide increased temperature uniformity over the array due to power dissipation during switching by the switching waveforms applied to the electrode tracks, wherein the resistance in an intermediate section of said at least one electrode track is greater than the resistance in two end sections of the electrode track, the two end sections being located operatively among the switching elements.

2. An array according to claim 1, wherein the resistance of said at least one electrode track varies along the length of the electrode track by virtue of the fact that at least one section of the electrode track has a greater transverse width than at least one other section of the electrode track.

3. An array according to claim 1, wherein the resistance of said at least one electrode track varies along the length of the electrode track by virtue of the fact that at least one section of the electrode track has a greater metallization thickness than at least one other section of the electrode track.

4. An array according to claim 1, which is a matrix display, wherein at least parts of the electrode tracks are made of transparent material.

5. An array according to claim 4, wherein said at least one electrode track comprises a main track portion of transparent material and a supplementary track portion of non-transparent material and of a greater conductivity which runs alongside, and is in electrical contact with, the main track portion.

6. An array according to claim 5, wherein the resistance of said at least one electrode track varies along the length of the electrode track by virtue of the fact that the main track portion and/or the supplementary track portion of at least one section of the electrode track has a greater transverse width than the corresponding portion of at least one other section of the electrode track.

7. An array according to claim 5, wherein the resistance of said at least one electrode track varies along the length of the electrode track by virtue of the fact that the main track portion and/or the supplementary track portion of at least one section of the electrode track has a greater metallization thickness than the corresponding portion of at least one other section of the electrode track.

8. An array according to claim 1, wherein at least one of the sets of electrode tracks comprises a first subset of electrode tracks having end connection points at one edge of the array for connection to drive circuitry for applying respective switching waveforms to the electrode tracks of the first subset by way of said end connection points, and a second subset of electrode tracks interleaved with the electrode tracks of the first subset and having end connection points at the opposite edge of the array for connection to drive circuitry for applying respective switching waveforms to the electrode tracks of the second subset by way of said end connection points.

9. A ferroelectric liquid crystal device incorporating an addressable matrix array, said array comprising an addressable matrix of switching elements, a first set of electrode tracks on one side of the matrix, and a second set of electrode tracks on the other side of the matrix, the first and second sets of electrode tracks crossing one another at the locations of the switching elements and the switching elements being switchable by the application of respective switching waveforms to the first and second sets of electrode tracks, and at least one of the electrode tracks having a resistance which varies along the length of the electrode track in order to provide increased temperature uniformity over the array due to power dissipation during switching by the switching waveforms applied to the electrode tracks, wherein the resistance in an intermediate section of said at least one electrode track is greater than the resistance in two end sections of the electrode track, the two end sections being located operatively among the switching elements.