Ferroelectric storage device

• US 5,999,438 A
• Filed: 05/11/1998
• Issued: 12/07/1999
• Est. Priority Date: 05/12/1997
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Ohsawa, Tosimasa
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US09/075,346
• Time in Patent Office: 575 Days
• Field of Search: 365/145, 365/149, 365/189.07
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 11/5657 using ferroelectric storage elements

Abstract

A ferroelectric storage device enabling an increase of capacity without a major increase in the chip size by use of multi-level data. At the time of a write operation, one of four types of potential based on the 2 bits of data input to the I/O terminal is selectively supplied from a potential generator to a bit line through a data line. The potential is supplied to one of the electrodes of a ferroelectric capacitor where one of four types of residual polarization states is selectively produced at the ferroelectric. By this, 4-level data is stored in a single memory cell. At the time of a read operation, the potential of the bit line is compared with three reference potentials at an output data generator to discriminate the stored data.

Claims

1. A ferroelectric storage device comprising:

word lines;

bit lines;

ferroelectric capacitors;

transistors switching said bit lines and one of the electrodes of said ferroelectric capacitors selectively to a connected state and disconnected state; and

a potential generating means for supplying 2ⁿ (n is an integer not less than "2") number of different types of potentials to said bit lines according to input data at the time of writing data.

2. A ferroelectric storage device as set forth in claim 1, further comprising output data generating means for comparing potentials generated at said bit lines with (2ⁿ -1) number of different types of reference potentials to discriminate the stored data.

3. A ferroelectric storage device as set forth in claim 2, further comprising

a plurality of switching means provided corresponding to said bit lines and connecting said bit lines to at least one of said potential generating means and said output data generating means and

a column address decoder for instructing connection to a switching means selected according to a column address of a cell to be accessed.

4. A ferroelectric storage device as set forth in claim 3, further comprising a row address decoder for supplying a predetermined potential to a bit line selected according to a row address of a cell to be accessed.

5. A ferroelectric storage device as set forth in claim 1, wherein said ferroelectric capacitors are arranged near the points of intersection of said word lines and bit lines to form a matrix.

6. A ferroelectric storage device as set forth in claim 1, wherein each of said ferroelectric capacitors comprises ((Pb,La)(Zr,Ti)O₃) or (Pb(Zr,Ti)O₃).

7. A ferroelectric storage device as set forth in claim 1, wherein each of said ferroelectric capacitors comprises Bi₂ SrTa₂ O₉.

8. A ferroelectric storage device comprising:

word lines;

bit lines;

ferroelectric capacitors;

transistors switching said bit lines and one of the electrodes of said ferroelectric capacitors selectively to a connected state and disconnected state;

a potential generating means for supplying 2ⁿ (n is an integer not less than "2") number of different types of potentials to said bit lines according to input data at the time of writing data; and

a discrimination means for comparing potentials generated at said bit lines with (2ⁿ -1) number of different types of reference potentials to discriminate the stored data.

9. A ferroelectric storage device as set forth claim 8, further comprising:

a plurality of switching means provided corresponding to said bit lines and connecting said bit lines to at least one of said potential generating means and said discrimination means and

a column address decoder for instructing connection to a switching means selected according to a column address of a cell to be accessed.

10. A ferroelectric storage device as set forth in claim 9, wherein each of said ferroelectric capacitors comprises ((Pb,La)(Zr,Ti)O₃) or (Pb(Zr,Ti)O₃).

11. A ferroelectric storage device as set forth in claim 9, wherein each of said ferroelectric capacitors comprises Bi₂ SrTa₂ O₉.