Ferroelectric memory using ferroelectric reference cells
First Claim
1. An integrated memory circuit comprising:
- an array of ferroelectric memory cells;
a multiplexed sense amplifier coupled to the array for sensing and amplifying data stored on the ferroelectric memory cells;
a first and a second reference circuit coupled to the array for providing a reference voltage that is compared to a voltage representative of data stored on the ferroelectric memory cells using the multiplexed sense amplifier; and
an alternate reference voltage circuit coupled to the first reference circuit for providing a reference voltage which is substantially stable over time, wherein the alternate reference voltage circuit includes a non-remnant capacitor circuit coupled to a voltage regulator.
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Accused Products
Abstract
A random access memory circuit is described which uses single ferroelectric memory cells to store data. The ferroelectric memory cells can be selectively read using reference cells to generate a reference voltage which is compared to a voltage representative of data stored on the memory cell using a multiplexed sense amplifier. In using two ferroelectric reference cells in which one contains a logical 0 polarization, and the other contains a logical 1 polarization, a single-ended reference voltage can be generated on a reference bit line. A ferroelectric memory cell can then be read by comparing the voltage on its corresponding bit line to the reference bit line using the sense amplifier. The content of the memory cell being read and the content of the reference cells can be rewritten on the same clock cycles to save on access time.
105 Citations
16 Claims
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1. An integrated memory circuit comprising:
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an array of ferroelectric memory cells; a multiplexed sense amplifier coupled to the array for sensing and amplifying data stored on the ferroelectric memory cells; a first and a second reference circuit coupled to the array for providing a reference voltage that is compared to a voltage representative of data stored on the ferroelectric memory cells using the multiplexed sense amplifier; and an alternate reference voltage circuit coupled to the first reference circuit for providing a reference voltage which is substantially stable over time, wherein the alternate reference voltage circuit includes a non-remnant capacitor circuit coupled to a voltage regulator. - View Dependent Claims (2)
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3. An integrated memory circuit comprising:
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an array of ferroelectric memory cells; a multiplexed sense amplifier coupled to the array for sensing and amplifying data stored on the ferroelectric memory cells; a first and a second reference circuit coupled to the array for providing a reference voltage that is compared to a voltage representative of data stored on the ferroelectric memory cells using the multiplexed sense amplifier; and an alternate reference voltage circuit coupled to the first reference circuit providing a reference voltage which is substantially stable over time, wherein the reference voltage circuit includes a non-remnant capacitor circuit which is coupled to a voltage regulator and which comprises; a conductor line having a line capacitance; and one or more capacitors selectively coupled to the conductor line via access devices. - View Dependent Claims (4, 5, 6, 7)
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8. An integrated memory circuit comprising:
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an array of one or more ferroelectric memory cells; multiplexed sense amplifier means for comparing signals representative of data stored on at least one of the ferroelectric memory cells to a reference voltage and providing an output voltage representative of the stored data; first and second reference means for providing the reference voltage to the sense amplifier means; and alternate reference voltage means coupled to the first reference circuit for providing a reference voltage which is substantially stable over time.
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9. An integrated memory circuit comprising:
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an array of ferroelectric memory cells; a first and a second reference circuit coupled to the array for providing a reference voltage, wherein the first and second reference circuits each comprise one or more ferroelectric reference cells; an alternate reference voltage circuit coupled to the first reference circuit for providing a reference voltage which is substantially stable over time, wherein the reference voltage circuit includes a non-remnant capacitor circuit coupled to a voltage regulator; and a multiplexed sense amplifier coupled to the array and to the first, second, and alternate reference voltage circuits for comparing signals representing data stored on the ferroelectric memory cells to the reference voltage of either the first reference circuit, the second reference circuit, or the alternate reference voltage circuit.
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10. An integrated memory circuit comprising:
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an array of ferroelectric memory cells; a first and a second reference circuit coupled to the array for providing a reference voltage, wherein the first and second reference circuits each comprise an even number of ferroelectric reference cells, with a first one-half of the ferroelectric reference cells polarized in one logical state and a second one-half of the ferroelectric reference cells polarized in an opposite logical state; and an alternate reference voltage circuit coupled to the first reference circuit for providing a reference voltage which is substantially stable over time, wherein the reference voltage circuit includes a non-remnant capacitor circuit coupled to a voltage regulator; and a multiplexed sense amplifier coupled to the array and to the first, second, and alternate reference voltage circuits for comparing signals representing data stored on the ferroelectric memory cells to the reference voltage of either the first reference circuit, the second reference circuit, or the alternate reference voltage circuit. - View Dependent Claims (11, 12)
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13. An integrated memory circuit comprising:
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an array of ferroelectric memory cells; a first and a second reference circuit coupled to the array for providing a reference voltage, wherein each reference circuit comprises an even number of ferroelectric reference cells, with a first one-half of the ferroelectric reference cells polarized in one logical state and a second one-half of the ferroelectric reference cells polarized in an opposite logical state; an alternate reference voltage circuit coupled to the first reference circuit for providing a reference voltage which is substantially stable over time, wherein the reference voltage circuit includes a non-remnant capacitor circuit coupled to a voltage regulator; and a multiplexed sense amplifier coupled to the array and to the first, second, alternate reference voltage circuits for comparing signals representing data stored on the ferroelectric memory cells to the reference voltage of either the first reference circuit, the second reference circuit, or the alternate reference voltage circuit.
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14. A computer system comprising:
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a processor; and a memory device coupled to the processor, wherein the processor defines memory access cycles, the memory device comprising; an array of one or more ferroelectric memory cells; multiplexed sense amplifier means for comparing signals representative of data stored on at least one of the ferroelectric memory cells to a reference voltage and providing an output voltage representative of the stored data; first and second reference means for providing the reference voltage to the sense amplifier means; and alternate reference voltage means coupled to the first reference circuit for providing a reference voltage which is substantially stable over time. - View Dependent Claims (15)
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16. A computer system comprising:
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a processor; and a memory device coupled to the processor, wherein the processor defines memory access cycles, the memory device comprising; an array of ferroelectric memory cells arranged according to a folded bit line architecture including two or more columns with staggered cells; a multiplexed sense amplifier coupled to the array for sensing and amplifying data stored on the ferroelectric memory cells; a first and a second reference circuit coupled to the array for providing a reference voltage that is compared to a voltage representative of data stored on the ferroelectric memory cells using the multiplexed sense amplifier, wherein the first and second reference circuits each comprise an even number of ferroelectric reference cells, with a first half of the ferroelectric reference cells polarized in one logical state and a second half of the ferroelectric reference cells polarized in an opposite logical state; and an alternate reference voltage circuit coupled to the first reference circuit providing a reference voltage which is substantially stable over time, wherein the reference voltage circuit includes a non-remnant capacitor circuit coupled to a voltage regulator.
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Specification