Nonvolatile semiconductor memory device and writing and erasing method of the same

• US 5,999,444 A
• Filed: 08/31/1998
• Issued: 12/07/1999
• Est. Priority Date: 09/02/1997
• Status: Expired due to Term

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Hayashi, Yutaka, Fujiwara, Ichiro
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US09/144,199
• Time in Patent Office: 463 Days
• Field of Search: 365/185.02, 365/185.18, 365/185.23
• US Class Current: 365/185.02
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written

Abstract

A nonvolatile semiconductor memory device and writing method of the same having a planarly dispersed charge storing means, which improve the programming disturbance characteristic, wherein gate electrodes of a plurality of memory elements are connected to a plurality of word lines, source regions or drain regions are connected with a common line (for example, a bit line or a source line) which crosses the word lines in an electrically insulated state, and the memory device includes a write inhibit voltage supplying means for supplying a source region and/or drain region of a memory element connected to the selected word line with a reverse bias voltage placing the source/drain region in a reverse bias state to the channel forming region via the common line and a non-selected word line biasing means for supplying a non-selected word line with a voltage in the polarity placing the non-selected word, line in a reverse bias state to the channel forming region.

Claims

1. A nonvolatile semiconductor memory device comprising a plurality of memory elements formed in the vicinity of the surface of a substrate, a plurality of word lines for driving the memory elements, and a plurality of bit lines, each of said plurality of memory elements including:

a semiconductor channel forming region formed in the vicinity of the surface of the substrate,

a source region in contact with the channel forming region in the vicinity of the surface of the substrate,

a drain region in contact with the channel forming region at a position facing the source region in the vicinity of the surface of the substrate,

a gate insulating film including a tunnel insulating film formed on the channel forming region,

a conductive gate electrode formed on the gate insulating film, and

a charge storing means which is provided on the tunnel insulating film and in the gate insulating film and is planarly discrete to the other neighboring charge storing means in the gate insulating film;

the gate electrodes of the plurality of memory elements being respectively connected to the plurality of word lines;

the source region or the drain region of each of the memory elements being connected to a common line in the bit direction electrically insulated from each of the plurality of word lines and intersecting the word lines; and

said memory device further comprising;

a write inhibit voltage applying means for applying a reverse bias voltage via the common line to the source region and/or drain region of the memory element having a gate electrode connected to a word line selected when writing data, the reverse bias voltage being a voltage by which the source region and/or drain region becomes reverse biased relative to the channel forming region; and

a non-selected word line biasing means for applying a voltage to a non-selected word line in the polarity of the reverse bias state to the channel forming region when writing data and biasing the gate electrode to the channel forming region to a value less than the write inhibit voltage.

2. A nonvolatile semiconductor memory device as set forth in claim 1, wherein the write inhibit voltage applying means supplies the reverse bias voltage to the source region and/or drain region so as to bias it to a voltage where the memory element connected to the selected word line will not be erroneously written and/or erased.

3. A nonvolatile semiconductor memory device as set forth in claim 1, wherein the non-selected word line biasing means biases the non-selected word line in the polarity becoming a reverse bias state to the channel forming region to a voltage where the memory element connected to the non-selected word line will not be erroneously written and/or erased.

4. A nonvolatile semiconductor memory device as set forth in claim 1, wherein the absolute value of at least the reverse bias voltage supplied to the drain region is larger than the absolute value of the voltage supplied by the non-selected word line biasing means.

5. A nonvolatile semiconductor memory device as set forth in claim 1, wherein the write inhibit voltage applying means applies an identical reverse bias voltage to both of the source region and the drain region.

6. A nonvolatile semiconductor memory device as set forth in claim 5, wherein the absolute value of the reverse bias voltage common to the source region and the drain region is larger than the absolute value of the voltage applied to the non-selected word line.

7. A nonvolatile semiconductor memory device as set forth in claim 1, wherein in the memory element, depletion layers extend from the source region of the memory element and the drain region of the memory element to the channel forming region where they merge when the reverse bias voltage is applied in a state where the gate electrode of the memory element is at the same potential as the channel forming region.

8. A nonvolatile semiconductor memory device as set forth in claim 1, wherein the gate length of the memory element is shorter than the gate length when the reverse bias voltage is applied in a state where the gate electrode of the memory element is in the same potential as the channel forming region of the memory element and depletion layers extend from the source region of the memory element and the drain region of the memory element to the channel forming region of the memory element and they just merge.

9. A nonvolatile semiconductor memory device as set forth in claim 1, wherein the gate length of a memory element is not more than 0.2 μ

m.

10. A nonvolatile semiconductor memory device as set forth in claim 1, wherein the nonvolatile memory device comprises:

source lines commonly connecting the source regions in the bit line direction and supplied with the reverse bias voltage,

bit lines commonly connecting the drain regions in the bit line direction and supplied with the reverse bias voltage, and

word lines commonly connecting the gate electrodes in the word line direction and supplied with a voltage in the polarity becoming a reverse bias state to the channel forming regions;

the write inhibit voltage supplying means connected to the source lines and the bit lines; and

the non-selected word line biasing means connected to non-selected word lines.

11. A nonvolatile semiconductor memory device as set forth in claim 10, wherein:

each of the source lines comprises a sub-source line to which the source region is connected and a main source line;

each of the bit lines comprises a sub-bit line to which the drain region is connected and a main bit line;

the memory device further comprises selection transistors, each of the transistors being positioned between the sub-source line and the main source line and between the sub-bit line and the main bit line; and

the reverse bias voltage supplied through the selection transistor from the main bit line side.

12. A nonvolatile semiconductor memory device as set forth in claim 1, further comprising a plurality of bit direction line shaped element isolation regions arranged at predetermined intervals from each other in the surface of the substrate and

the common line being arranged in a detouring manner on the element isolation regions so as to be connected on one of the source regions or drain regions and to avoid the other of the source regions or drain regions.

13. A nonvolatile semiconductor memory device as set forth in claim 12, wherein:

the plurality of element isolation regions form parallel stripes in shape;

the source regions and drain regions are formed with contact holes self-aligned by side wall insulating layers formed on side walls of the word lines; and

a common line arranged in a detouring manner over the element isolation regions is meander placed while commonly connecting the one regions.

14. A nonvolatile semiconductor memory device as set forth in claim 1, wherein the charge storing means does not have conductivity as an overall plane facing the channel forming region at least when there is no movement of charge to or from the charge storing means.

15. A nonvolatile semiconductor memory device as set forth in claim 14, wherein the gate insulating film includes a tunnel insulating film on the channel forming layer and a nitride film formed on the tunnel insulating film.

16. A nonvolatile semiconductor memory device as set forth in claim 15, wherein the gate insulating film includes a top oxide film positioned between the nitride film and the gate electrode.

17. A nonvolatile semiconductor memory device as set forth in claim 14, wherein the gate insulating film includes a tunnel insulating film on the channel forming region and an oxynitride film formed on the tunnel insulating film.

18. A nonvolatile semiconductor memory device as set forth in claim 17, wherein the gate insulating film includes a top oxide film positioned between the oxynitride film and the gate electrode.

19. A nonvolatile semiconductor memory device as set forth in claim 14, wherein the gate insulating film includes a tunnel insulating film on the channel forming layer and, as the charge storing means, small particle size semiconductor or conductors formed on the tunnel insulating film and mutually insulated from each other, the particle size less than 10 nanometeres.

20. A nonvolatile semiconductor memory device as set forth in claim 19, wherein the gate insulating film includes an oxide film including the small particle size semiconductors or conductors.

21. A nonvolatile semiconductor memory device as set forth in claim 20, wherein the gate insulating film includes a top oxide film positioned between the oxide film and the gate electrode.

22. A nonvolatile semiconductor memory device as set forth in claim 14, wherein the gate insulating film includes a tunnel insulating film on the channel forming region and a finely divided floating gate formed on the tunnel insulating film as the charge storing means.

23. A nonvolatile semiconductor memory device as set forth in claim 22, wherein the gate insulating film includes an oxide film including the finely divided floating gate.

24. A nonvolatile semiconductor memory device as set forth in claim 23, wherein the gate insulating film includes a top oxide film positioned between the oxide film and the gate electrode.

25. A writing method in a nonvolatile semiconductor memory device in which a plurality of memory elements formed in the vicinity of the surface of a substrate are arranged in a word line direction and a bit line direction, each of the plurality of memory elements in the nonvolatile semiconductor memory device comprising:

a semiconductor channel forming region formed in the vicinity of the surface of the substrate, a source region in contact with the channel forming region in the vicinity of the surface of the substrate, a drain region in contact with the channel forming region at a position facing the source region in the vicinity of the surface of the substrate, a gate insulating film including a tunnel insulating film formed on the channel forming region, a conductive gate electrode formed on the gate insulating film, and a charge storing means which is provided on the tunnel insulating film and in the gate insulating film and is planarly discrete to the other neighboring charge storing means in the gate insulating film;

the gate electrodes of the plurality of memory elements being respectively connected to the plurality of word lines; and

the source region or the drain region of each of the memory elements being connected to a common line in the bit direction electrically insulated from each of the word lines and intersecting the word lines;

the writing method in the nonvolatile semiconductor memory device including the steps of;

applying a voltage to a non-selected word line in the polarity by which the non-selected word line becomes in a reverse bias state to the channel forming region when writing data; and

applying a reverse bias voltage via the common line to the source region and/or drain region of the memory element having a gate electrode connected to a word line selected when writing data, the reverse bias voltage being a voltage by which the source region and/or drain region becomes reverse biased relative to the channel forming region to thereby reduce write and/or erase inhibit disturb with respect to the non-selected memory element wherein the absolute value of at least the reverse bias voltage applied to the drain region is higher than the absolute value of the voltage supplied to the non-selected word line.

26. A writing method in a nonvolatile semiconductor memory device as set forth in claim 25, wherein said reverse bias voltage to the source region and/or drain region is a voltage where the memory element connected to the selected word line will not be erroneously written and/or erroneously erased.

27. A writing method in a nonvolatile semiconductor memory device as set forth in claim 25, wherein said voltage of the non-selected word line in the polarity becoming the non-selected word line in a reverse bias state to the channel forming region, is a voltage where the memory element connected to the non-selected word line will not be erroneously written and/or erroneously erased.

28. A writing method in a nonvolatile semiconductor memory device as set forth in claim 25, wherein said voltage of the non-selected gate electrode is not more than an inhibit voltage to the source and/or drain region.

29. A writing method in a nonvolatile semiconductor memory device as set forth in claim 25, wherein when supplying the reverse bias voltage, the same voltage is supplied to both of the source region and the drain region.

30. A writing method in a nonvolatile semiconductor memory device as set forth in claim 25, wherein the absolute value of the reverse bias voltage common to the source region and the drain region is higher than the absolute value of the voltage supplied to the non-selected word line.

31. A writing method in a nonvolatile semiconductor memory device as set forth in claim 25, wherein in the memory element, depletion layers extend from the source region and the drain region to the channel forming region where they merge when the reverse bias voltage is supplied in a state where the gate electrode is in the same potential as the channel forming region.

32. A writing method in a nonvolatile semiconductor memory device as set forth in claim 25, wherein the gate length of the memory element is shorter than the gate length when the reverse bias voltage is supplied in a state where the gate electrode of the memory element is in the same potential as the channel forming region and depletion layers extend from the source region and the drain region to the channel forming region and they just merge.

33. A writing method in a nonvolatile semiconductor memory device as set forth in claim 25, wherein the gate length of a memory element is not more than 0.2 μ

m.

34. A writing method in a nonvolatile semiconductor memory device as set forth in claim 25, wherein:

the nonvolatile memory device comprises;

source lines commonly connecting the source regions in the bit line direction,

bit lines commonly connecting the drain regions in the bit line direction, and

word lines commonly connecting the gate electrodes in the word line direction;

the reverse bias voltage supplied through the source lines and/or the bit lines; and

the voltage in a direction becoming a reverse bias to the channel forming regions supplied through the word lines.

35. A writing method in a nonvolatile semiconductor memory device as set forth in claim 34, wherein:

each of the source lines comprises a sub source line to which the source region is connected and a main source line;

each of the bit lines comprises a sub bit line to which the drain region is connected and a main bit line;

the memory device further comprises selection transistors between the sub-source line and main source line and between the sub bit line and main bit line; and

the reverse bias voltage is supplied through the selection transistor from the main bit line side.

36. A writing method in a nonvolatile semiconductor memory device as set forth in claim 34, wherein:

the nonvolatile semiconductor memory device comprises a plurality of bit line direction shaped element isolation regions formed at intervals from each other in the surface of the substrate and

the common line is arranged in a detouring manner on the element isolation regions so as to be connected to one of the source regions and drain regions and avoid the other regions.

37. A writing method in a nonvolatile semiconductor memory device as set forth in claim 36, wherein:

the plurality of element isolation regions form parallel stripes in shape;

the source regions and drain regions are formed with contact holes self-aligned by side wall insulating layers formed on side walls of the word lines; and

the common line arranged in a detouring manner over the element isolation regions is meander placed while commonly connecting the one regions.

38. A writing method in a nonvolatile semiconductor memory device as set forth in claim 25 wherein the charge storing means does not have conductivity as an overall plane facing the channel forming region at least when there is no movement of charge to or from the charge storing means.

39. A writing method in a nonvolatile semiconductor memory device as set forth in claim 38, wherein the gate insulating film includes a tunnel insulating film on the channel forming region and a nitride film formed on the tunnel insulating film.

40. A writing method in a nonvolatile semiconductor memory device as set forth in claim 38, wherein the gate insulating film includes a tunnel insulating film on the channel forming region and an oxynitride film formed on the tunnel insulating film.

41. A writing method in a nonvolatile semiconductor memory device as set forth in claim 38, wherein the gate insulating film includes a tunnel insulating film on the channel forming layer and, as the charge storing means, small particle size semiconductor or conductors formed on the tunnel insulating film and mutually insulated from each other, the particle size less than 10 nanometers.

42. A writing method in a nonvolatile semiconductor memory device as set forth in claim 38, wherein the gate insulating film includes a tunnel insulating film on the channel forming region and a finely divided floating gate formed on the tunnel insulating film as the charge storing means.

43. A writing method in a nonvolatile semiconductor memory device as set forth in claim 25, further including the steps of:

supplying the non-selected word line with a voltage becoming the non-selected word line in the back bias state;

supplying the source region and/or drain region of the memory element connected to the selected word line with the back bias voltage through the common line; and

supplying the selected word line with a programming voltage.

51. A writing method in a nonvolatile semiconductor memory device as set forth in claim 38, wherein the gate insulating film includes a tunnel insulating film on the channel forming region and a finely divided floating gate formed on the tunnel insulating film as the charge storing means.

44. A nonvolatile semiconductor memory device comprising a plurality of memory elements formed in the vicinity of the surface of a substrate, a plurality of word lines for driving the memory elements, and a plurality of bit lines, each of said plurality of memory elements including:

a semiconductor channel forming region formed in the vicinity of the surface of the substrate,

a source region in contact with the channel forming region in the vicinity of the surface of the substrate,

a drain region in contact with the channel forming region at a position facing the source region in the vicinity of the surface of the substrate,

a gate insulating film including a tunnel insulating film formed on the channel forming region,

a conductive gate electrode formed on the gate insulating film, and

a charge storing means which is provided on the tunnel insulating film and in the gate insulating film and is planarly discrete to the other neighboring charge storing means in the gate insulating film;

the gate electrodes of the plurality of memory elements being respectively connected to the plurality of word lines;

the source region or the drain region of each of the memory elements being connected to a common line in the bit direction electrically insulated from each of the plurality of word lines and intersecting the word lines;

a plurality of bit direction line shaped element isolation regions arranged at predetermined intervals from each other in the surface of the substrate;

the common line being arranged in a detouring manner over the element isolation regions so as to be connected on one of the source regions or drain regions and to avoid the other of the source regions or drain regions; and

said memory device further comprising;

a write inhibit voltage applying means for applying a reverse bias voltage via the common line to the source region and/or drain region of the memory element having a gate electrode connected to a word line selected when writing data, the reverse bias voltage being a voltage by which the source region and/or drain region becomes reverse biased relative to the channel forming region; and

a non-selected word line biasing means for applying a voltage to a non-selected word line in the polarity of the reverse bias state to the channel forming region when writing data.

45. A nonvolatile semiconductor memory device as set forth in claim 44, wherein:

the plurality of element isolation regions form parallel stripes in shape;

the source regions and drain regions are formed with contact holes self-aligned by side wall insulating layers formed on side walls of the word line; and

a common line arranged in a detouring manner over the element isolation regions is meander placed while commonly connecting the one regions.

46. A writing method in a nonvolatile semiconductor memory device in which a plurality of memory elements formed in the vicinity of the surface of a substrate are arranged in a word line direction and a bit line direction, each of the plurality of memory elements in the nonvolatile semiconductor memory device comprising:

a semiconductor channel forming region formed in the vicinity of the surface of the substrate, a source region in contact with the channel forming region in the vicinity of the surface of the substrate, a drain region in contact with the channel forming region at a position facing the source region in the vicinity of the surface of the substrate, a gate insulating film including a tunnel insulating film formed on the channel forming region, a conductive gate electrode formed on the gate insulating film, and a charge storing means which is provided on the tunnel insulating film and in the gate insulating film and is planarly discrete to the other neighboring charge storing means in the gate insulating film;

the gate electrodes of the plurality of memory elements being respectively connected to the plurality of word lines; and

the source region or the drain region of each of the memory elements being connected to a common line in the bit direction electrically insulated from each of the word lines and intersecting the word lines;

the source regions and the drain regions formed with contact holes self-aligned by side wall insulation layers formed on side wall of the word lines;

a plurality of bit line direction shaped element isolation regions formed at intervals from each other in the surface of the substrate, the plurality of element isolation regions forming parallel stripes in shape; and

the common line arranged in a detouring manner over the element isolation regions so as to be connected to one of the source regions and drain regions and avoid the other regions and the common line arranged being meander placed while commonly connecting the one regions;

the writing method in the nonvolatile semiconductor memory device including the steps of;

applying a voltage to a non-selected word line in the polarity which becomes the non-selected word line in a reverse bias state to the channel forming region when writing data; and

applying a reverse bias voltage via the common line to the source region and/or drain region of the memory element having a gate electrode connected to a word line selected when writing data, the reverse bias voltage being a voltage by which the source region and/or drain region becomes reverse biased relative to the channel forming region to thereby reduce write and/or erase inhibit disturb with respect to the non-selected memory element.

47. A writing method in a nonvolatile semiconductor memory device in which a plurality of memory elements formed in the vicinity of the surface of a substrate are arranged in a word line direction and a bit line direction, each of the plurality of memory elements in the nonvolatile semiconductor memory device comprising:

a semiconductor channel forming region formed in the vicinity of the surface of the substrate, a source region in contact with the channel forming region in the vicinity of the surface of the substrate, a drain region in contact with the channel forming region at a position facing the source region in the vicinity of the surface of the substrate, a gate insulating film including a tunnel insulating film formed on the channel forming region, a conductive gate electrode formed on the gate insulating film, and a charge storing means which is provided on the tunnel insulating film and in the gate insulating film and is planarly discrete to the other neighboring charge storing means in the gate insulating film;

the gate electrodes of the plurality of memory elements being respectively connected to the plurality of word lines; and

the source region or the drain region of each of the memory elements being connected to a common line in the bit direction electrically insulated from each of the word lines and intersecting the word lines;

the charge storing means not having conductivity as an overall plane facing the channel forming region at least when there is no movement of charge to or from the charge storing means;

the writing method in the nonvolatile semiconductor memory device including the steps of;

applying a voltage to a non-selected word line in the polarity which becomes the non-selected word line in a reverse bias state to the channel forming region when writing data; and

applying a reverse bias voltage via the common line to the source region and/or drain region of the memory element having a gate electrode connected to a word line selected when writing data, the reverse bias voltage being a voltage by which the source region and/or drain region becomes reverse biased relative to the channel forming region to thereby reduce write and/or erase inhibit disturb with respect to the non-selected memory element.

48. A writing method in a nonvolatile semiconductor memory device as set forth in claim 47, wherein the gate insulating film includes a tunnel insulating film on the channel forming region and a nitride film formed on the tunnel insulating film.

49. A writing method in a nonvolatile semiconductor memory device as set forth in claim 47, wherein the gate insulating film includes a tunnel insulating film on the channel forming region and an oxynitride film formed on the tunnel insulating film.

50. A writing method in a nonvolatile semiconductor memory device as set forth in claim 47, wherein the gate insulating film includes a tunnel insulating film on the channel forming layer and, as the charge storing means, small particle size semiconductor or conductors formed on the tunnel insulating film mutually insulated from each other and having a particle size of less than 10 nanometers.

52. A writing method in a nonvolatile semiconductor memory device in which a plurality of memory elements formed in the vicinity of the surface of a substrate are arranged in a word line direction and a bit line direction, each of the plurality of memory elements in the nonvolatile semiconductor memory device comprising:

a semiconductor channel forming region formed in the vicinity of the surface of the substrate, a source region in contact with the channel forming region in the vicinity of the surface of the substrate, a drain region in contact with the channel forming region at a position facing the source region in the vicinity of the surface of the substrate, a gate insulating film including a tunnel insulating film formed on the channel forming region, a conductive gate electrode formed on the gate insulating film, and a charge storing means which is provided on the tunnel insulating film and in the gate insulating film and is planarly discrete to the other neighboring charge storing means in the gate insulating film;

the gate electrodes of the plurality of memory elements being respectively connected to the plurality of word lines; and

the source region or the drain region of each of the memory elements being connected to a common line in the bit direction electrically insulated from each of the word lines and intersecting the word lines;

the writing method in the nonvolatile semiconductor memory device including the steps of;

applying a voltage to a non-selected word line in the polarity which becomes the non-selected word line in a reverse bias state to the channel forming region when writing data;

applying a reverse bias voltage via the common line to the source region and/or drain region of the memory element having a gate electrode connected to a word line selected when writing data, the reverse bias voltage being a voltage by which the source region and/or drain region becomes reverse biased relative to the channel forming region to thereby reduce write and/or erase inhibit disturb with respect to the non-selected memory element;

supplying the non-selected word line with a voltage becoming the non-selected word line in the reverse bias state;

supplying the source region and/or drain region of the memory element connected to the selected word line with the reverse bias voltage through the common line; and

supplying the selected word line with a programming voltage.