Method and apparatus for stress testing a semiconductor memory
First Claim
1. An apparatus for testing a semiconductor memory having a sense device coupled to one of a plurality of pairs of complementary bit conductors within a memory sub-array of the semiconductor memory through a pair of isolation devices, the apparatus comprising:
- another pair of isolation devices for selectively coupling the sense device to another one of the pairs of complementary bit conductors in the memory sub-array; and
circuitry coupled to both pairs of isolation devices for activating the isolation devices at about the same time.
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Accused Products
Abstract
Circuitry stress tests a Dynamic Random Access Memory (DRAM) by connecting a sense amplifier of the DRAM to at least two pairs of complementary bitlines within the same sub-array of the DRAM through two pairs of isolation transistors activated at substantially the same time. The circuitry thus provides for the stress testing of memory cells associated with sense amplifiers connected to only one sub-array within a DRAM or other semiconductor memory. The apparatus also provides an alternative to conventional methods for stress testing memory cells associated with sense amplifiers connected to more than one sub-array within a DRAM or other semiconductor memory.
17 Citations
17 Claims
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1. An apparatus for testing a semiconductor memory having a sense device coupled to one of a plurality of pairs of complementary bit conductors within a memory sub-array of the semiconductor memory through a pair of isolation devices, the apparatus comprising:
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another pair of isolation devices for selectively coupling the sense device to another one of the pairs of complementary bit conductors in the memory sub-array; and circuitry coupled to both pairs of isolation devices for activating the isolation devices at about the same time. - View Dependent Claims (2, 3)
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4. A semiconductor memory comprising:
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a memory sub-array; a plurality of pairs of complementary bit conductors coupled to the memory sub-array; a sense device; a pair of isolation devices coupled between the sense device and one of the pairs of complementary bit conductors; another pair of isolation devices coupled between the sense device and another one of the pairs of complementary bit conductors; and circuitry coupled to both pairs of isolation devices for activating the isolation devices at about the same time. - View Dependent Claims (5, 6, 7, 8)
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9. An electronic system comprising an input device, an output device, a memory device, and a processor device coupled to the input, output, and memory devices, at least one of the input, output, memory, and processor devices including a semiconductor memory comprising:
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a memory sub-array; a plurality of pairs of complementary bit conductors coupled to the memory sub-array; a sense device; a pair of isolation devices coupled between the sense device and one of the pairs of complementary bit conductors; another pair of isolation devices coupled between the sense device and another one of the pairs of complementary bit conductors; and circuitry coupled to both pairs of isolation devices for activating the isolation devices at about the same time. - View Dependent Claims (10, 11, 12, 13)
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14. A semiconductor wafer on which is fabricated a semiconductor memory comprising:
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a memory sub-array; a plurality of pairs of complementary bit conductors coupled to the memory sub-array; a sense device; a pair of isolation devices coupled between the sense device and one of the pairs of complementary bit conductors; another pair of isolation devices coupled between the sense device and another one of the pairs of complementary bit conductors; and circuitry coupled to both pairs of isolation devices for activating the isolation devices at about the same time. - View Dependent Claims (17)
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- 15. A method of testing a semiconductor memory, the method comprising selectively coupling a sense device of the semiconductor memory to at least two pairs of complementary bit conductors in the same memory sub-array of the semiconductor memory at about the same time.
Specification