Direct sequence spread spectrum method, computer-based product, apparatus and system tolerant to frequency reference offset

• US 5,999,561 A
• Filed: 09/15/1997
• Issued: 12/07/1999
• Est. Priority Date: 05/20/1997
• Status: Expired due to Term

• Current Assignee: Globalstar Incorporated, M&FC Holding, LLC
• Original Assignee: Sanconix Inc.
• Inventors: Reed, Marc L., Hwang, Charles A., Rouquette, Robert E., Sanderford, H. Britton Jr., Naden, Gary A., Reiser, Dale E.
• Primary Examiner(s): VO, DON NGUYEN
• Application Number:
  US08/929,891
• Time in Patent Office: 813 Days
• Field of Search: 375/206, 375/208, 375/209, 375/210, 370/320, 370/335, 370/342
• US Class Current: 375/142
• CPC Class Codes: H04B 1/707 using direct sequence modulation

Abstract

A method, apparatus, computer-based product and system employs a digital receiver (or transceiver) to receive, digitize and process a direct sequence spread spectrum signal using efficient, low-cost digital signal processing components. A radio front end portion of the receiver receives and digitizes the signal, and a digital signal processing portion downconverts and despreads the signal by applying a pseudorandom noise (PN) code, used at a transmitter to spread a data signal contained in the direct sequence spread spectrum signal, to the received signal. In order to initially align, and maintain alignment of, the PN code with the direct sequence spread spectrum signal, a timing and state control mechanism is included that provides time reference correction information to the signal processing components of the receiver. This time reference correction information allows the receiver to be compatible with transmitters using inaccurate frequency references which impart a significant frequency ambiguity in the received signal. Additional features include computer-based synchronization methods and mechanisms suitable for use for low performance digital signal processors and employ power management mechanisms that enable long-term operation using battery power. The power management mechanisms enable the receiver to operate in a network setting, over the course of multiple years off battery power, with similar receivers, transmitters and transceiver that communicate with one another using direct sequence spread spectrum signals.

Claims

1. A direct sequence spread spectrum system comprising:

a transmitter configured to transmit a direct sequence spread spectrum signal, comprising,

a transmitter frequency reference that produces a frequency with a predetermined accuracy,

a spreading code generator that generates said spreading code with a predetermined transmit signal chipping frequency error and modulates a data signal with said spreading code to produce a spread data signal having a frequency error component attributable to said predetermined accuracy of the transmitter frequency reference,

a radio frequency generator that produces a radio frequency signal having a frequency error attributable to said predetermined accuracy of said frequency reference, and

a transmitter signal combiner configured to receive and combine said radio frequency signal and said spread data signal to produce the direct sequence spread spectrum signal; and

a receiver configured to extract said data signal from said direct sequence spread spectrum signal transmitted from said transmitter, comprising,

a receiver frequency reference that produces a frequency with another predetermined accuracy,

a code generator that generates said spreading code, said spreading code having a receiver chipping frequency error component,

a receiver radio frequency generator configured to produce a downconversion signal derived from said frequency of said receiver frequency reference, said downconversion signal having a frequency error attributable to said predetermined accuracy of said frequency from said receiver frequency reference,

a receiver signal combiner that combines the direct sequence spread spectrum signal with the downconversion signal to produce a translated signal said translated signal including said frequency error of said transmitter radio frequency signal error component and the downconversion signal error component,

a sampling device that samples the translated signal at a frequency that is four times a center frequency of the translated signal to produce a sampled signal,

a despreading and downconverting combiner coupled to the code generator and configured to despread and downconvert the sampled signal, comprising,

a sign inversion mechanism that inverts a sign of respective samples of said sampled signal so as to despread and downconvert said sampled signal, and

at least one data signal detector configured to detect the data signal, a composite bandwidth of said at least one data signal detector being in a range including a data signal bandwidth and a frequency uncertainty bandwidth of said signal due to at least the predetermined accuracy of the transmitter frequency reference.

2. The system of claim 1, wherein said receiver comprises at least one of a single channel receiver and a multi-channel receiver.

3. The system of claim 1, wherein said receiver further comprises an internal transmitter configured to transmit a signal therefrom, said receiver and said internal transmitter combining to provide a transceiver function.

4. The system of claim 1, wherein said predetermined accuracy of said transmitter frequency reference causing said frequency error of the radio frequency signal and said transmit signal chipping frequency error to be not independent of one another, said transmit signal chipping frequency error inducing a performance degradation at said receiver due to a time dependent reposition error.

5. The system of claim 1, wherein said receiver further comprises a computer-readable medium whose contents cause a processor to implement said despreading and downconverting combiner.

6. The system of claim 1, wherein:

said transmitter frequency reference comprises means for producing the frequency with the predetermined accuracy;

said spreading code generator of said generator comprises means for generating said spreading code;

said radio frequency generator comprises means for producing said radio frequency signal;

said transmitter signal combiner comprises means for producing the direct sequence spread spectrum signal;

said receiver frequency reference comprises means for producing said frequency with another predetermined accuracy;

said code generator of said receiver comprises means for generating said spreading code having said receiver chipping frequency error component;

said receiver radio frequency generator comprises means for producing said downconversion signal;

said receiver signal combiner comprises means for combining the direct sequence spread spectrum signal with the downconversion signal to produce the translated signal;

said sampling device comprises means for sampling the translated signal at the frequency that is four times the center frequency of the translated signal so as to produce the sampled signal; and

said despreading and downconverting combiner comprises means for despreading and downconverting the sampled signal, comprising,

means for sign inverting the sign of respective samples of said sampled signal so as to despread and downconvert said sampled signal, and

means for detecting the data signal, the composite bandwidth of said at least one data signal detector being in the range including the data signal bandwidth and the frequency uncertainty bandwidth of said signal due to at least the predetermined accuracy of the transmitter frequency reference.

7. The system of claim 1 wherein, said receiver further comprises:

a plurality of antennas;

a diversity reception control mechanism, comprising,

a selection mechanism for selecting one of said plurality of antennas after determining which of said antennas provides a signal that yields a correlation result meeting a selection threshold; and

a frequency diversity determination mechanism configured to determine at which of a plurality of frequencies a transmitted signal is centered and receive the transmitted signal at the frequency after making the determination.

8. A method for communicating a direct sequence spread spectrum signal, comprising the steps of:

transmitting from a transmitter a direct sequence spread spectrum signal, comprising substeps of,

producing with a transmitter frequency reference a frequency with a predetermined accuracy,

generating with a spreading code generator a spreading code with a predetermined transmit signal chipping frequency error and modulating a data signal with said spreading code to produce a spread data signal having a frequency error component attributable to said predetermined accuracy of the transmitter frequency reference,

generating with a radio frequency generator a radio frequency signal having a frequency error attributable to said predetermined accuracy of said frequency reference, and

combining with a transmitter signal combiner said radio frequency signal and said spread data signal to produce the direct sequence spread spectrum signal; and

extracting at a receiver said data signal from said direct sequence spread spectrum signal transmitted from said transmitter, comprising substeps of,

producing at a receiver frequency reference a frequency with another predetermined accuracy,

generating with a code generator said spreading code, said spreading code having a receiver chipping frequency error component,

producing with a receiver radio frequency generator a downconversion signal derived from said frequency of said receiver frequency reference, said downconversion signal having a frequency error attributable to said predetermined accuracy of said frequency from said receiver frequency reference,

combining with a receiver signal combiner the direct sequence spread spectrum signal with the downconversion signal to produce a translated signal, said translated signal including said frequency error of said transmitter radio frequency signal error component and the downconversion signal error component,

sampling with a sampling device the translated signal at a frequency that is four times a center frequency of the translated signal to produce a sampled signal,

despreading and downconverting with a despreading and downconverting combiner the sampled signal, comprising substeps of,

inverting with a sign inversion mechanism a sign of respective samples of said sampled signal so as to despread and downconvert said sampled signal, and

detecting with at least one data signal detector the data signal, a composite bandwidth of said at least one data signal detector being in a range including a data signal bandwidth and a frequency uncertainty bandwidth of said signal due to at least the predetermined accuracy of the transmitter frequency reference.

9. A method for simultaneously downconverting and applying a spreading code to a direct sequence spread spectrum signal, said spreading code having previously been used by a transmitter to spread a data signal at a predetermined chip rate, comprising the steps of:

sampling said signal at a sampling rate, Fs, to produce data samples, wherein said sampling rate, Fs, being four times a center frequency of said sampled signal, Fs being a multiple, M, of the code chip rate, M having a value of at least 1 and representing an oversample ratio;

downconverting and despreading respective samples in a signal signing step comprising,

inverting a sign value of one of said data samples if a product of a downconversion coefficient and a despreading code coefficient is negative, not inverting if said product is positive, and zeroing said data sample if said product is zero.

10. The method of claim 9, wherein said downconverting and despreading step comprises:

assigning a value of 1 to respective downconversion coefficient that coincide in time with a positive maximum value of a sinusoid having a frequency equal to the center frequency of said sampled signal,

assigning a value of 0 to respective downconversion coefficients that coincide in time with a zero crossing at said sinusoid; and

assigning a value of -1 to respective downconversion coefficients that coincide in time with a negative maximum of said sinusoid.

11. The method of claim 10 wherein said downconverting and despreading step comprises:

assigning a value of 1 to respective spreading code coefficients that correspond in time with chips of said spreading code that are at a first state; and

assigning a value of -1 to respective spreading code coefficients that correspond in time with chips of said spreading code that are at a second state.

12. A receiver configured to simultaneously downconvert and apply a spreading code to a direct sequence spread spectrum signal, said spreading code having previously been used by a transmitter to spread a data signal at a predetermined chip rate, comprising:

means for sampling said signal at a sampling rate, Fs, to produce data samples, wherein said sampling rate, Fs, being four times a center frequency of said sampled signal, Fs being a multiple, M, of the code chip rate, M having a value of at least 1 and representing an oversample ratio;

means for downconverting and despreading respective samples in a signal sample signing means comprising,

means for inverting a sign value of one of said data samples if a product of a downconversion coefficient and a despreading code coefficient is negative, not inverting if said product is positive, and zeroing said data sample if said product is zero.

13. A receiver, comprising:

means for simultaneously downconverting and applying a spreading code to a direct sequence spread spectrum signal, said spreading code having previously been used by a transmitter to spread a data signal at a predetermined chip rate;

means for sampling said signal at a sampling rate, Fs, to produce data samples, wherein said sampling rate, Fs, being four times a center frequency of said sampled signal, Fs being a multiple, M, of the code chip rate, M having a value of at least 1 and representing an oversample ratio;

means for downconverting and despreading respective samples in a single signing step comprising,

means for inverting a sign value of one of said data samples if a product of a downconversion coefficient and a despreading code coefficient is negative, not inverting if said product is positive, and zeroing said data sample if said product is zero.

14. A receiver comprising:

a despreader configured to simultaneously downconvert and apply a spreading code to a direct sequence spread spectrum signal, said spreading code having previously been used by a transmitter to spread a data signal at a predetermined chip rate,

a signal sampler configured to sample said signal at a sampling rate, Fs, to produce data samples, wherein said sampling rate, Fs, being four times a center frequency of said sampled signal, Fs being a multiple, M, of the code chip rate, M having a value of at least 1 and representing an oversample ratio;

a memory device configured to store said data samples,

a processing device configured to retrieve said data samples and then downconvert and despread respective samples in a signal signing step comprising,

a program stored in processor memory that causes the processor to invert a sign value of one of said data samples if a product of a downconversion coefficient and a despreading code coefficient is negative, not inverting if said product is positive, and zeroing said data sample if said product is zero.

15. A receiver that reduces signal loss caused by decimation of a direct sequence spread spectrum signal transmitted from a transmitter, said decimation having associated therewith a predetermined bandwidth and response characteristic, said response characteristic imparting a greater amount of attenuation in a first part of said bandwidth than in a second part of said bandwidth, comprising:

means for receiving said signal using a receiver frequency reference, said transmitter employing a transmitter frequency reference where the tolerances of the respective references combine to create a predetermined signal position uncertainty range in which said signal is positioned prior to demodulation of the signal;

means for decimating said signal with a decimation operator to reduce a sample rate of said signal;

means for subdividing said predetermined signal position uncertainty range bandwidth into a plurality of candidate downconversion frequency bands;

means for changing an amount by which a downconversion operator translates the signal toward the second part of said bandwidth, where said amount is set by assuming the signal is placed in one of the plurality of candidate downconversion frequency bands, attempting to correlate said signal with a spreading code used to spread the signal at the transmitter and means for determining whether correlation is achieved; and

means for repeating sequentially said correlate said signal with a spreading code used to spread the signal at the transmitter and means for changing for the other channels and stopping said means for repeating when said means for determining determines that correlation is achieved.

16. The receiver of claim 15, wherein:

said means for repeating comprises said means for changing for the other channels until the means for changing has been performed for all of the channels;

said means for determining comprises,

means for deciding that correlation is achieved after the means for changing has operated on all of the channels, and

means for determining which of the plurality of candidate downconversion frequency bands yielded the greatest correlation result.

17. A method employed in a direct sequence spread spectrum receiver for avoiding false pseudorandom noise code synchronization detection caused by spontaneous in-band interference, said receiver having a plurality of channel filters arranged within a predetermined bandwidth corresponding to a frequency uncertainty range due to frequency offset in respective frequency references in a transmitter and said receiver, comprising the steps of:

attempting to despread said signal by applying the pseudorandom noise code to said signal and outputting a stream of digital samples;

applying said digital samples to said channel filters;

determining respective energy amounts within said channel filters;

identifying which channel filter has a maximum energy amount therein;

determining a composite average power for a portion of all remaining channel filters except for the channel filter identified as having the maximum energy and a pair of channel filters being adjacent thereto;

determining if said maximum energy exceeds said average energy by at least a predetermined amount, and deciding that an alignment of said pseudorandom noise code and said signal is within two chip intervals of said pseudorandom noise code so that coarse synchronization is achieved if said maximum energy exceeds said average energy by at least a predetermined amount; and

performing fine search correlation and data demodulation if coarse synchronization is achieved and returning to said attempting step where said signal and pseudorandom noise code are shifted relative to one another before being applied to one another.

18. The method of claim 17, wherein said step of determining a composite average power comprises determining a composite average power for all remaining channels.

19. A direct sequence spread spectrum receiver configured to avoid false pseudorandom noise code synchronization detection caused by spontaneous in-band interference, said receiver having a plurality of channels arranged within a predetermined bandwidth corresponding to a frequency uncertainty range due to frequency offset in respective frequency references in a transmitter and said receiver, comprising:

means for attempting to despread said signal by applying the pseudorandom noise code to said signal and outputting a stream of digital samples;

means for applying said digital samples to said channel filters;

means for determining respective energy amounts within said channel filters;

means for identifying which channel filter has a maximum energy amount therein;

means for determining a composite average power for a portion of all remaining channels except for the channel filter identified as having the maximum energy and a pair of channels being adjacent thereto;

means for determining if said maximum energy exceeds said average energy by at least a predetermined amount, and deciding that an alignment of said pseudorandom noise code and said signal is within two chip intervals of said pseudorandom noise code so that course synchronization is achieved if said maximum energy exceeds said average energy by at least a predetermined amount; and

means for performing fine search correlation and data demodulation if course synchronization is achieved and returning control to said means for attempting where said signal and pseudorandom noise code are shifted relative to one another before being applied to one another.

20. A direct sequence spread spectrum receiver configured to avoid false pseudorandom noise code synchronization detection caused by spontaneous in-band interference, said receiver having a plurality of channels arranged within a predetermined bandwidth corresponding to a frequency uncertainty range due to frequency offset in respective frequency references in a transmitter and said receiver, comprising:

a despreader configured to despread said signal by applying the pseudorandom noise code to said signal and outputting a stream of digital samples;

an application device configured to apply said digital samples to said channel filters;

an energy determination device configured to determine respective energy amounts within said channel filters;

a maximum energy detection device configured to identify which channel filter has a maximum energy amount therein;

a composite power device configured to determine a composite average power for a portion of all remaining channels except for the channel filter identified as having the maximum energy and a pair of channels being adjacent thereto;

a comparison device configured to determine if said maximum energy exceeds said average energy by at least a predetermined amount, and deciding that an alignment of said pseudorandom noise code and said signal is within two chip intervals of said pseudorandom noise code so that course synchronization is achieved if said maximum energy exceeds said average energy by at least a predetermined amount; and

a device configured to perform fine search correlation and data demodulation if course synchronization is achieved and returning to said attempting step where said signal and pseudorandom noise code are shifted relative to one another before being applied to one another.

21. A direct sequence spread spectrum receiver that avoids false pseudorandom noise code synchronization detection caused by spontaneous in-band interference, comprising:

a frequency reference;

a plurality of channel filters arranged within a predetermined bandwidth corresponding to a frequency uncertainty range due to frequency offset in said frequency reference and another frequency reference used by a transmitter;

means for receiving a signal by said receiver;

means for attempting to despread said signal by applying the pseudorandom noise code to said signal and outputting a stream of digital samples;

means for applying said digital samples to said channel filters;

means for determining respective energy amounts within said channel filters;

means for identifying which channel filter has a maximum energy amount therein;

means for determining a composite average power for a portion of all remaining channel filters except for the channel filter identified as having the maximum energy and a pair of channel filters being adjacent thereto;

means for determining if said maximum energy exceeds said average energy by at least a predetermined amount, and deciding that an alignment of said pseudorandom noise code and said signal is within two chip intervals of said pseudorandom noise code so that coarse synchronization is achieved if said maximum energy exceeds said average energy by at least a predetermined amount; and

means for performing fine search correlation and data demodulation if coarse synchronization is achieved and returning to said means for attempting where said signal and pseudorandom noise code are shifted relative to one another before being applied to one another.

22. A method in a direct sequence spread spectrum receiver for avoiding false pseudorandom noise code synchronization detection caused by spontaneous in-band interference, said receiver having a plurality of channel filters arranged within a predetermined bandwidth corresponding to a frequency uncertainty range due to frequency offset in respective frequency references in a transmitter and said receiver, comprising the steps of:

receiving a signal by said receiver;

attempting to despread said signal by applying the pseudorandom noise code to said signal and outputting a stream of digital samples;

applying said digital samples to said channel filters;

determining respective energy amounts within said channel filters;

identifying the channel filter having a maximum energy amount therein;

identifying another channel filter of said channel filters which has a second largest energy, said another channel filter not being one of a pair of channel filters being adjacent to the channel identified as having the maximum energy amount;

determining if said maximum energy exceeds said second largest energy by at least a predetermined amount; and

performing fine search correlation and data demodulation if coarse synchronization is achieved, and returning to said attempting step where said signal and pseudorandom noise code are shifted relative to one another before being applied to one another.

23. A direct sequence spread spectrum receiver comprising:

means for avoiding false pseudorandom noise code synchronization detection caused by spontaneous in-band interference, including a plurality of channel filters arranged within a predetermined bandwidth corresponding to a frequency uncertainty range due to frequency offset in respective frequency references in a transmitter and said receiver, comprising,

means for attempting to despread said signal by applying the pseudorandom noise code to said signal and outputting a stream of digital samples;

means for applying said digital samples to said channel filters;

means for determining respective energy amounts within said channel filters;

means for identifying the channel filter having a maximum energy amount therein;

means for identifying another channel filter of said channel filters which has a second largest energy, said another channel filter not being one of a pair of channel filters being adjacent to the channel filter identified as having the maximum energy amount;

means for determining if said maximum energy exceeds said second largest energy by at least a predetermined amount; and

means for performing fine search correlation and data demodulation if course synchronization is achieved, and returning to said means for attempting where said signal and pseudorandom noise code are shifted relative to one another before being applied to one another.

24. A direct sequence spread spectrum receiver comprising:

a despreader that applies the pseudorandom noise code to said signal and outputting, a stream of digital samples;

a plurality of channel filters arranged within a predetermined bandwidth corresponding to a frequency uncertainty range due to frequency offset in respective frequency references in a transmitter and said receiver, wherein said channel filters being configured to operate on said digital samples;

a device to determine the respective energy amounts within said channel filters;

a device to identify the channel filter having a maximum energy amount therein;

a device to identify another channel filter of said channel filters which has a second largest energy, said another channel filter not being one of a pair of channel filters being adjacent to the channel filter identified as having the maximum energy amount;

a device to determine if said maximum energy exceeds said second largest energy by at least a predetermined amount; and

a device to perform fine search correlation and data demodulation if course synchronization is achieved, and returning to said attempting step where said signal and pseudorandom noise code are shifted relative to one another before being applied to one another.

25. A direct sequence spread spectrum receiver that avoids false pseudorandom noise code synchronization detection caused by spontaneous in-band interference, comprising:

a frequency reference;

a plurality of channel filters arranged within a predetermined bandwidth corresponding to a frequency uncertainty range due to frequency offset in said frequency reference and another frequency reference used by a transmitter;

means for receiving a signal by said receiver;

means for attempting to despread said signal by applying the pseudorandom noise code to said signal and outputting a stream of digital samples;

means for applying said digital samples to said channel filters;

means for determining respective energy amounts within said channel filters;

means for identifying the channel filter having a maximum energy amount therein;

means for identifying another channel filter of said channel filters which has a second largest energy, said another channel filter not being one of a pair of channel filters being adjacent to the channel identified as having the maximum energy amount;

means for determining if said maximum energy exceeds said second largest energy by at least a predetermined amount; and

means for performing fine search correlation and data demodulation if coarse synchronization is achieved, and returning to said attempting step where said signal and pseudorandom noise code are shifted relative to one another before being applied to one another.

26. A method for reducing code phase correlation error in a direct sequence spread spectrum receiver after a direct sequence spread spectrum signal and a pseudorandom code used to spread the signal at a transmitter have been aligned to one another within one pseudorandom code chip interval, comprising the steps of:

sampling said signal at a predetermined sampling rate and producing signal samples;

despreading said signal by applying said pseudorandom code to said signal samples and obtaining a despread signal;

determining a power of said despread signal, said power being an indication of how closely said signal and said pseudorandom code are aligned to one another;

identifying respective powers of despread signal for other relative pseudorandom code phases by,

despreading said signal by shifting a relative position of said signal and said pseudorandom code by less than said pseudorandom code chip interval,

determining said another of said respective powers of said despread signal, and

repeating said identifying step until all of said respective powers have been identified;

determining an operational positional alignment between said pseudorandom code and said signal samples by performing a center of mass operation on said power and said respective powers; and

despreading said signal using said operational positional alignment previously determined and demodulating said despread signal.

27. The method of claim 26 wherein said step of determining an operational positional alignment comprises the steps of:

retarding a relative position of the pseudorandom code relative to the signal samples by at least 1/2 of said chip interval relative to an initial alignment position that caused said receiver to determine that said pseudorandom code and said signal are aligned to within one chip interval;

despreading said signal by applying said pseudorandom code to said samples and obtaining a despread signal;

computing and storing a power of said despread signal, said power being an indication of how closely said signal and said pseudorandom code are aligned to one another;

advancing the relative position by a fractional chip step, to compute and store one of the relative signal powers; and

continuing said advancing step until said relative position of the pseudorandom code relative to the signal samples meets or exceeds one chip relative to said position in said retarding step; and

determining said operational positional alignment between said pseudorandom code and said signal samples by performing a center of mass operation on said power and said relative powers.

28. The method of claim 27, wherein:

said retarding step and said advancing step combine to provide relative position alignments of -1/2, -1/4, +1/4 and +1/2 of a chip, and said determining a power step provides an initial signal power for a 0 relative position, thereby providing a first set of five signal powers corresponding respectively to relative position alignments of -1/2, -1/4, 0, +1/4 and +1/2 of a chip;

said performing a center of mass operation step comprises,

calculating a first center of mass of said first set of five signal powers,

determining if the first center of mass is greater than +1/4 chip offset, and if so performing the advancing step to identify respective signal powers for +3/4 and +1 chip offset and computing a second center of mass on a second set of five signal powers associated with the 0 +1/4, +1/2, +3/4, and +1 relative position alignments,

determining if the first center of mass is less than -1/4 chip offset, and if so performing the advancing step in a retarding direction so as to identify respective signal powers for -3/4 and -1 chip offset and computing a third center of mass on a third set of five signal powers associated with the -1, -3/4, -1/2, -1/4, and 0 relative position alignments; and

adjusting the relative phase to the operational positional alignment using said second center of mass if said first center of mass is determined to be greater than +1/4 chip offset, and adjusting the relative phase to the operational positional alignment using said third center of mass if said second center of mass is determined to be less than -1/4 chip offset.

29. The method of claim 27, wherein:

said sampling step comprises,

decimating said signal samples to reduce a sample rate of said samples to coincide with a chip code rate of said pseudorandom noise code, said samples being a first set of samples,

obtaining a second set of samples offset by 1/4 of a chip interval of said code chip rate relative to said first set of samples;

said second set of samples being provided at said sample rate,

obtaining a third set of samples offset by 1/2 of a chip interval of said code chip rate relative to said first set of samples, said third set of samples being provided at said sample rate, and

obtaining a fourth set of samples offset by 3/4 of a chip interval of said code chip rate relative to said first set of samples, said fourth set of samples being provided at said sample rate;

said retarding step and said advancing step combine to provide relative position alignments of -1, 0, and +1 of a chip, and further comprising the steps of,

determining respective signal powers of said second set of samples for chip offsets of -3/4 and +1/4 relative to said relative position alignment for said first set of samples;

determining respective signal powers of said third set of samples for chip offsets of -1/2 and +1/2 relative to said relative position alignment for said first set of samples;

determining respective signal powers of said fourth set of samples for chip offsets of -1/4 and +3/4 relative to said relative position alignment for said first set of samples;

wherein

said performing a center of mass operation step comprises,

calculating said center of mass using said signal powers associated with said chip set offsets for said first set of samples, second set of samples, third set of samples and fourth set of samples.

30. The method of claim 26, wherein:

said sampling step comprises sampling said signal at a multiple M of a chipping rate of said pseudorandom code;

decimating said samples to reduce a sample rate of said samples to coincide with the chipping rate;

adjusting the relative position by at least -1/2 of a code chip interval;

obtaining other data samples after said adjusting step, repeatedly determining a signal power of said other data samples, and adjusting the relative position farther by +1/M;

repeating said steps of obtaining, repeatedly determining and adjusting until said relative position is offset by at least +1/2 of a code chip interval;

determining a center of mass for said signal powers for respective of said relative positions;

if the center of mass is greater than 1/M of a chip code interval,

collecting and measuring a set of additional signal powers for additional relative positions at a predetermined fractional increment, set of additional signal powers comprising elements between 0 and 1, and

determining another center of mass using said additional signal powers; and

adjusting said relative position by said center of mass if said determining step determines that said center of mass is not greater than 1/M of a chip code interval and adjusting said relative position by said another center of mass if said determining step determines that said center of mass is greater than a 1/M chip code interval.

31. The method of claim 26, wherein:

said sampling step comprises sampling said signal at by an amount corresponding to a product of N and M, where N is a length of said pseudorandom code and M is a multiple of a chipping rate of said pseudorandom code;

obtaining sets of data samples, respective sets corresponding to respective of plural fractional chip interval length relative position adjustments; and

despreading respective of said sets of samples using a receiver spreading code generator configured to produce a code chip sample at a rate of (2×

M)+1, comprising the steps of,

offsetting the relative position by an amount and direction corresponding to -1 of a chip interval,

despreading one of the sets of samples and obtaining a corresponding signal power,

advancing the relative position by an amount corresponding to 1/M of a code chip interval,

despreading another of the sets of samples and obtaining a corresponding signal power,

repeating said advancing and despreading another steps until the relative position corresponds to +1 of a code chip interval.

32. A direct sequence spread spectrum receiver with means for reducing code phase correlation error after a direct sequence spread spectrum signal and a pseudorandom code used to spread the signal at a transmitter have been aligned to one another within one pseudorandom code chip interval, comprising the steps of:

means for sampling said signal at a predetermined sampling rate and producing signal samples;

means for despreading said signal by applying said pseudorandom code to said signal samples and obtaining a despread signal;

means for determining a power of said despread signal, said power being an indication of how closely said signal and said pseudorandom code are aligned to one another;

means for identifying respective powers of despread signal for other reative pseudorandom code phases including,

means for despreading said signal by shifting a relative position of said signal and said pseudorandom code by less than said pseudorandom code chip interval,

means for determining said another of said respective powers of said despread signal, and

means for repeating said identifying step until all of said respective powers have been identified;

means for determining an operational positional alignment between said pseudorandom code and said signal samples by performing a center of mass operation on said power and said respective powers; and

means for despreading said signal using said operational positional alignment previously determined and demodulating said despread signal.

33. A direct sequence spread spectrum receiver comprising:

a sampler for sampling said signal at a predetermined sampling rate and producing signal samples;

a despreader for despreading said signal by applying said pseudorandom code to said signal samples and obtaining a despread signal;

a power determination device for determining a power of said despread signal, said power being an indication of how closely said signal and said pseudorandom code are aligned to one another;

a power comparison device for identifying respective powers of despread signal for other relative pseudorandom code phases using,

a despreading device for despreading said signal by shifting a relative position of said signal and said pseudorandom code by less than said pseudorandom code chip interval, and

a device for determining said another of said respective powers of said despread signal;

a device for determining an operational positional alignment between said pseudorandom code and said signal samples by performing a center of mass operation on said power and said respective powers; and

a device for despreading said signal using said operational positional alignment previously determined and demodulating said despread signal.

34. A direct sequence spread spectrum receiver for reducing code phase correlation error therein after a pseudorandom code used to spread the signal at a transmitter has been aligned to a locally produced pseudorandom code within one pseudorandom code chip interval, comprising:

means for sampling said signal at a predetermined sampling rate and producing signal samples;

means for despreading said signal by applying said pseudorandom code to said signal samples and obtaining a despread signal;

means for determining a power of said despread signal, said power being an indication of how closely said signal and said pseudorandom code are aligned to one another;

means for identifying respective powers of despread signal for other relative pseudorandom code phases comprising,

means for despreading said signal by shifting a relative position of said signal and said pseudorandom code by less than said pseudorandom code chip interval,

means for determining another of said respective powers of said despread signal, and

means for repeating said identifying until all of said respective powers have been identified;

means for determining an operational positional alignment between said pseudorandom code and said signal samples by performing a center of mass operation on said power and said respective powers; and

means for despreading said signal using said operational positional alignment previously determined and demodulating said despread signal.

35. The receiver of claim 34 wherein said means for determining an operational positional alignment comprises:

means for retarding a relative position of the pseudorandom code relative to the signal samples by at least 1/2 of said chip interval relative to an initial alignment position that caused said receiver to determine that said pseudorandom code and said signal are aligned to within one chip interval;

means for computing and storing another signal power;

means for advancing the relative position by a fractional chip step, to compute one of the other signal powers; and

means for continuing said means for advancing until said relative position of the pseudorandom code relative to the signal samples meets or exceeds one chip relative to said position in said means for retarding; and

means for determining said operational positional alignment between said pseudorandom code and said signal samples by performing a center of mass operation on said power and said relative powers.

36. The receiver of claim 35, wherein:

said means for retarding and said means for advancing combine to provide relative position alignments of -1/2, -1/4, +1/4 and +1/2 of a chip, and said determining a power step provides an initial signal power for a 0 relative position, thereby providing a first set of five signal powers corresponding respectively to relative position alignments of -1/2, -1/4, 0, +1/4 and +1/2 of a chip;

said means for performing a center of mass operation step comprises,

means for calculating a first center of mass of said first set of five signal powers,

means for determining if the first center of mass is greater than +1/4 chip offset, and if so performing the advancing step to identify respective signal powers for +3/4 and +1 chip offset and computing a second center of mass on a second set of five signal powers associated with the 0 +1/4, +1/2, +3/4, and +1 relative position alignments,

means for determining if the first center of mass is less than -1/4 chip offset, and if so performing the means for advancing a retarding direction so as to identify respective signal powers for -3/4 and -1 chip offset and computing a third center of mass on a third set of five signal powers associated with the -1, -3/4, -1/2, -1/4, and 0 relative position alignments; and

means for adjusting the relative phase to the operational positional alignment using said second center of mass if said first center of mass is determined to be greater than +1/4 chip offset, and adjusting the relative phase to the operational positional alignment using said third center of mass if said second center of mass is determined to be less than -1/4 chip offset.

37. The receiver of claim 35, wherein:

said means for sampling step comprises,

means for decimating said signal samples to reduce a sample rate of said samples to coincide with a chip code rate of said pseudorandom noise code, said samples being a first set of samples, comprising

means for obtaining a second set of samples offset by 1/4 of a chip interval of said code chip rate relative to said first set of samples;

said second set of samples being provided at said sample rate,

means for obtaining a third set of samples offset by 1/2 of a chip interval of said code chip rate relative to said first set of samples, said third set of samples being provided at said sample rate, and

obtaining a fourth set of samples offset by 3/4 of a chip interval of said code chip rate relative to said first set of samples, said fourth set of samples being provided at said sample rate;

said means for retarding and said means for advancing combine to provide relative position alignments of -1, 0, and +1 of a chip, and further comprising,

means for determining respective signal powers of said second set of samples for chip offsets of -3/4 and +1/4 relative to said relative position alignment for said first set of samples;

means for determining respective signal powers of said third set of samples for chip offsets of -1/2 and +1/2 relative to said relative position alignment for said first set of samples;

means for determining respective signal powers of said fourth set of samples for chip offsets of -1/4 and +3/4 relative to said relative position alignment for said first set of samples;

wherein

said means for performing a center of mass operation comprises,

means for calculating said center of mass using said signal powers associated with said chip set offsets for said first set of samples, second set of samples, third set of samples and fourth set of samples.

38. The receiver of claim 34, wherein:

said means for sampling comprises means for sampling said signal at a multiple M of a chipping rate of said pseudorandom code;

means for decimating said samples to reduce a sample rate of said samples to coincide with the chipping rate;

means for adjusting the relative position by at least -1/2 of a code chip interval;

means for obtaining other data samples after said means for adjusting, determining a signal power of said other data samples, and adjusting the relative position further by +1/M;

means for repeating said means for obtaining, determining and adjusting until said relative position is offset by at least +1/2 of a code chip interval;

means for determining a center of mass for said signal powers for respective of said relative positions;

if the center of mass is greater than 1/M of a chip code interval,

means for collecting and measuring a set of additional signal powers for additional relative positions at a predetermined fractional increment, set of additional signal powers comprising elements between 0 and 1, and

means for determining another center of mass using said additional signal powers; and

means for adjusting said relative position by said center of mass if said means for determining determines that said center of mass is not greater than 1/M of a chip code interval and adjusting said relative position by said another center of mass if said determining step determines that said center of mass is greater than a 1/M chip code interval.

39. The receiver of claim 34, wherein:

said means for sampling comprises means for sampling said signal at by an amount corresponding to a product of N and M, where N is a length of said pseudorandom code and M is a multiple of a chipping rate of said pseudorandom code;

means for obtaining sets of data samples, respective sets corresponding to respective of plural fractional chip interval length relative position adjustments; and

means for despreading respective of said sets of samples using a receiver spreading code generator configured to produce a code chip sample at a rate of (2×

M)+1, comprising,

means for offsetting the relative position by an amount and direction corresponding to -1 of a chip interval,

means for despreading one of the sets of samples and obtaining a corresponding signal power,

means for advancing the relative position by an amount corresponding to 1/M of a code chip interval,

means for despreading another of the sets of samples and obtaining a corresponding signal power,

means for repeating said means for advancing and means for despreading another until the relative position corresponds to +1 of a code chip interval.

40. A method for reducing code phase correlation error in a direct sequence spread spectrum receiver after a direct sequence spread spectrum signal and a pseudorandom code, used to spread the signal at a transmitter, have been determined by said receiver to be aligned to one another within one-half of a pseudorandom code chip interval, comprising the steps of:

sampling said signal at a predetermined sampling rate and producing signal samples;

performing a least-squares operation on signal powers associated with different fractional relative position offsets between said signal and pseudorandom code chip, comprising the steps of,

producing a pseudorandom code at a relative position being less than or equal to 1/2 of an initial code chip position when said receiver determined that said signal and said pseudorandom code are aligned;

identifying a signal power associated with said relative position,

producing at an advanced relative position the pseudorandom code, said pseudorandom code being advanced by a fractional chip step,

repeatedly identifying a signal power associated with the advanced relative position, and

repeating said steps of producing and repeatedly identifying until said relative position reaches or exceeds 1/2 chip beyond said initial code chip position,

determining a least-squares value of said signal powers and adjusting said relative position by said least-squares value if said value is less than a predetermined chip threshold;

performing a center of mass calculation on said signal powers and adjusting said relative position by a 1/2 chip offset if said determining step determines that said least-squares value is not less than said predetermined threshold;

readjusting said relative position by performing said step of performing the least-square operation for a second time and after performing at least one of said steps of determining a least-squares value and a performing a center of mass calculation; and

demodulating said signal after said readjusting step.

41. A direct sequence spread spectrum receiver that reduces code phase correlation error after a direct sequence spread spectrum signal and a pseudorandom code, used to spread the signal at a transmitter, have been determined by said receiver to be aligned to one another within one-half of a pseudorandom code chip interval, comprising:

means for sampling said signal at a predetermined sampling rate and producing signal samples;

means for performing a least-squares operation on signal powers associated with different fractional relative position offsets between said signal and pseudorandom code chip, means for producing a pseudorandom code at a relative position being less than or equal to 1/2 of an initial code chip position when said receiver determined that said signal and said pseudorandom code are aligned;

means for identifying a signal power associated with said relative position;

means for producing at an advanced relative position the pseudorandom code, said pseudorandom code being advanced by a fractional chip step;

means for identifying a signal power associated with the advanced relative position, means for successively returning control to said means for producing and means for identifying until said relative position reaches or exceeds 1/2 chip beyond said initial code chip position;

means for determining a least-squares value of said signal powers and adjusting said relative position by said least-squares value if said value is less than a predetermined chip threshold;

means for performing a center of mass calculation on said signal powers and adjusting said relative position by a 1/2 chip offset if said means for determining determines that said least-squares value is not less than said predetermined threshold;

means for readjusting said relative position by performing, the least-square operation for a second time and performing a center of mass calculation; and

means for demodulating said signal after processing by said means for readjusting.

42. A direct sequence spread spectrum receiver that reduces code phase correlation error after a direct sequence spread spectrum signal and a pseudorandom code, used to spread the signal at a transmitter, have been determined by said receiver to be aligned to one another within one-half of a pseudorandom code chip interval, comprising:

a sampling device for sampling said signal at a predetermined sampling rate and producing signal samples;

a processing device for performing a least-squares operation on signal powers associated with different fractional relative position offsets between said signal and pseudorandom code chip, comprising,

a code generation device configured to produce a pseudorandom code at a relative position being less than or equal to 1/2 of an initial code chip position when said receiver determined that said signal and said pseudorandom code are aligned;

a power identification device configured to identify a signal power associated with said relative position,

a chip advance device configured to produce at an advanced relative position the pseudorandom code, said pseudorandom code being advanced by a fractional chip step,

a signal power identification device configured to identify a signal power associated with the advanced relative position, and

a repeating device configured to repeat at least one previous processing operation until said relative position reaches or exceeds 1/2 chip beyond said initial code chip position,

a least-squares device configured to determine a least-squares value of said signal powers and adjust said relative position by said least-squares value if said value is less than a predetermined chip threshold;

a center of mass calculation device configured to perform a center of mass calculation on said signal powers and adjust said relative position by a 1/2 chip offset if said least-squares value is not less than said predetermined threshold;

a readjustment device configured to readjust said relative position by performing said the least-square operation for a second time and performing a center of mass calculation; and

a demodulation device configured to demodulate said signal after said device configured to readjust said relative position has processed said signal.

43. A direct sequence spread spectrum receiver for reducing code phase correlation error, after a direct sequence spread spectrum signal and a pseudorandom code, used to spread the signal at a transmitter, have been determined by said receiver to be aligned to one another within one-half of a pseudorandom code chip interval, comprising:

means for sampling said signal at a predetermined sampling rate and producing signal samples;

means for performing a least-squares operation on signal powers associated with different fractional relative position offsets between said signal and pseudorandom code chip, comprising,

means for producing a pseudorandom code at a relative position being less than or equal to 1/2 of an initial code chip position when said receiver determined that said signal and said pseudorandom code are aligned;

means for identifying a signal power associated with said relative position,

means for producing at an advanced relative position the pseudorandom code, said pseudorandom code being advanced by a fractional chip step,

means for repeatedly identifying a signal power associated with the advanced relative position, and

means for repeating said means for producing and means for repeatedly identifying until said relative position reaches or exceeds 1/2 chip beyond said initial code chip position,

means for determining a least-squares value of said signal powers and adjusting said relative position by said least-squares value if said value is less than a predetermined chip threshold;

means for performing a center of mass calculation on said signal powers and adjusting said relative position by a 1/2 chip offset if said means for determining determines that said least-squares value is not less than said predetermined threshold;

means for readjusting said relative position by using said means for performing the least-square operation for a second time and after using at least one of said means for determining a least-squares value and performing a center of mass calculation; and

means for demodulating said signal after processing in said readjusting means.

44. A method for removing a frequency uncertainty error at an output of a differential binary phase shift keyed direct sequence spread spectrum signal in a receiver, said frequency uncertainty caused in part by a frequency offset between a transmitter frequency reference and a receiver frequency reference, said signal after being despread having a complex Nyquist bandwidth being greater than or equal to said frequency uncertainty, comprising the steps of:

storing a first data bit of said signal;

multiplying a second data bit with a complex conjugate of the first data and producing a complex product;

decimating said complex product to a single complex sample C(n) per data bit interval so as to provide a resulting signal with a static phase angle being at least one of θ and

θ

+180 degrees;

removing said static phase angle with a decision feedback phase error canceler, comprising,

determining a complex number C.sub.θ

(n) having an angle being a resulting static phase error averaged over M previous bits;

translating the static phase error to 0 by multiplying C(n) with a complex conjugate of C.sub.θ

(n) and obtaining a multiplication result,

identifying a sign of a real part of said multiplication result and making a bit decision based thereon, and

update a C.sub.θ

average with C(n) multiplied with a sign of the second bit.

45. The method of claim 44, wherein said removing step comprises removing said static phase angle for the differential binary phase shift key direct sequence spread spectrum signal in which a plurality of data bits are contained within one code phase of said signal.

46. A direct sequence spread spectrum receiver that removes a frequency uncertainty error at an output of a differential binary phase shift keyed direct sequence spread spectrum signal in a receiver, said frequency uncertainty caused in part by a frequency offset between a transmitter frequency reference and a receiver frequency reference, said signal after being despread having a complex Nyquist bandwidth being greater than or equal to said frequency uncertainty, comprising:

means for storing a first data bit of said signal;

means for multiplying a second data bit with a complex conjugate of the first data and producing a complex product;

means for decimating said complex product to a single complex sample C(n) per data bit interval so as to provide a resulting signal with a static phase angle being at least one of θ and

θ

+180 degrees;

means for removing said static phase angle with a decision feedback phase error canceler, comprising,

means for determining a complex number C.sub.θ

(n) having an angle being a resulting static phase error averaged over M previous bits,

means for translating the static phase error to 0 by multiplying C.sub.θ

(n) with a complex conjugate of C.sub.θ

(n) and obtaining a multiplication result,

means for identifying a sign of a real part of said multiplication result and making a bit decision based thereon, and

means for update a C.sub.θ

average with C(n) multiplied with a sign of the second bit.

47. A direct sequence spread spectrum receiver that removes a frequency uncertainty error at an output of a differential binary phase shift keyed direct sequence spread spectrum signal, said frequency uncertainty caused in part by a frequency offset between a transmitter frequency reference and a receiver frequency reference, said signal after being despread having a complex Nyquist bandwidth being greater than or equal to said frequency uncertainty, comprising:

a storage device for storing a first data bit of said signal;

a multiplier device for multiplying a second data bit with a complex conjugate of the first data and producing a complex product;

a decimation device for decimating said complex product to a single complex sample C(n) per data bit interval so as to provide a resulting signal with a static phase angle being at least one of θ and

θ

+180 degrees;

a removal device for removing said static phase angle with a decision feedback phase error canceler, comprising,

a determination device for determining a complex number C.sub.θ

(n) having an angle being a resulting static phase error averaged over M previous bits;

a translation device for translating the static phase error to 0 by multiplying C.sub.θ

(n) with a complex conjugate of C.sub.θ

(n) and obtaining a multiplication result,

an identification device for identifying a sign of a real part of said multiplication result and making a bit decision based thereon, and

an update device for updating a C.sub.θ

average with C.sub.θ

(n) multiplied with a sign of the second bit.

48. A direct sequence spread spectrum receiver that removes a frequency uncertainty error at an output of a differential binary phase shift keyed signal, said frequency uncertainty caused in part by a frequency offset between a transmitter frequency reference and a receiver frequency reference, said signal after being despread having a complex Nyquist bandwidth being greater than or equal to said frequency uncertainty, comprising:

means for generating said frequency reference;

means for storing a first data bit of said signal;

means for multiplying a second data bit with a complex conjugate of the first data and producing a complex product;

means for decimating said complex product to a single complex sample C(n) per data bit interval so as to provide a resulting signal with a static phase angle being at least one of θ and

θ

+180 degrees;

means for removing said static phase angle with a decision feedback phase error canceler, comprising,

means for determining a complex number C.sub.θ

(n) having an angle being a resulting static phase error averaged over M previous bits;

means for translating the static phase error to 0 by multiplying C(n) with a complex conjugate of C.sub.θ

(n) and obtaining a multiplication result,

means for identifying a sign of a real part of said multiplication result and making a bit decision based thereon, and

means for update a C.sub.θ

average with C(n) multiplied with a sign of the second bit.

49. A method for distributing a decimation operation into plural stages in a direct sequence spread spectrum receiver, comprising:

receiving a direct sequence spread spectrum signal at said receiver, said signal having been spread at a transmitter with a spreading code of length N, N being divisible by a plurality of prime factors;

sampling said signal at a predetermined sampling rate;

producing said spreading code at said receiver;

decimating said signal in a first decimation stage by a first fraction of the sampling rate and providing a first decimated signal having a lower sample rate, wherein said first fraction is equal to one of said plurality of prime factors than said predetermined sample rate; and

decimating said decimated signal in a second decimation stage by another fraction of the sampling rate and providing a second decimated signal have a lower sample rate than said first decimated signal, wherein said another fraction is equal to another of said plurality of prime factors.

50. The method of claim 49, wherein said receiving step, comprises receiving said direct sequence spread spectrum receiver wherein said signal has been spread at a transmitter with a spreading code having at least one of a code length less than 100, being a 2^k -1 sequence, having prime factors being less than 10, but greater than 2.

51. The method of claim 49, wherein said sampling step comprises sampling said signal at a rate being an integer multiple of N.

52. The method of claim 49, wherein said step of decimating said signal in a first decimation stage comprises decimating before said signal has been despread with said spreading code and said decimating said decimated signal in a second decimation stage, comprising decimating after said despreading with said spreading signal.

53. The method of claim 52, wherein said step of decimating said decimated signal in a first decimation stage, comprises decimating by a decimation ratio of 4, and said decimating said decimated signal in a second decimation stage, comprising decimating by a decimation ratio of 10.5.

54. The method of claim 49, wherein said receiving step comprises receiving the direct sequence spread spectrum signal, said signal having been spread at the transmitter with a spread code of length N, where N complies with the requirement 2^k -1.

55. A direct sequence spread spectrum receiver that distributes a decimation operation into plural stages comprising:

means for receiving a direct sequence spread spectrum signal at said receiver said signal having been spread at a transmitter with a spreading code of length N, N being divisible by a plurality of prime factors;

means for sampling said signal at a predetermined sampling rate;

means for producing said spreading code at said receiver;

means for decimating said signal in a first decimation stage by a first fraction of the sampling rate and providing a first decimated signal having a lower sample rate than said predetermined sample rate; and

means for decimating said decimated signal in a second decimation stage by another fraction of the sampling rate and providing a second decimated signal have a lower sample rate than said first decimated signal, wherein because N being divisible by the plurality of prime factors being an enabling feature for separately performing said first decimation stage and said second decimation stage.

56. A direct sequence spread spectrum receiver that distributes a decimation operation into plural stages comprising:

a front-end device configured to receive a direct sequence spread spectrum signal at said receiver, said signal having been spread at a transmitter with a spreading code of length N, N being divisible by a plurality of prime factors;

a sampling device for sampling said signal at a predetermined sampling rate;

a code generating device for producing said spreading code at said receiver;

a first decimation device for decimating said signal in a first decimation stage by a first fraction of the sampling rate and providing a first decimated signal having a lower sample rate than said predetermined sample rate; and

a second decimation device for decimating said decimated signal in a second decimation stage by another fraction of the sampling rate and providing a second decimated signal have a lower sample rate than said first decimated signal, wherein because N being divisible by the plurality of prime factors being an enabling feature for separately performing said first decimation stage and said second decimation stage.

57. A direct sequence spread spectrum receiver having a plurality of decimation operators, comprising:

means for receiving a direct sequence spread spectrum signal at said receiver, said signal having been spread at a transmitter with a spreading code of length N, N being divisible by a plurality of prime factors;

means for sampling said signal at a predetermined sampling rate;

means for producing said spreading code at said receiver;

means for decimating said signal in a first decimation stage by a first fraction of the sampling rate and providing a first decimated signal having a lower sample rate than said predetermined sample rate, wherein said first fraction is equal to one of said plurality of prime factors; and

means for decimating said decimated signal in a second decimation stage by another fraction of the sampling rate and providing a second decimated signal have a lower sample rate than said first decimated signal, wherein said another fraction is equal to another of said plurality of prime factors.

58. A method for efficient synchronization of a direct sequence spread spectrum signal in a receiver, said signal being spread with a maximal length spreading code of length N at a transmitter, N being divisible by a plurality of prime factors, comprising the steps of:

receiving said signal;

digitizing said signal; and

correlating said spreading code with said signal by calculating a Fast Fourier transform with a predetermined number of computations, said predetermined number of computations being lower than a minimum number of calculations required to correlate another signal despread with another maximal length spreading code that is greater than or equal to 15 and divisible by a lesser number of prime factors than N.

59. A direct sequence spread spectrum receiver that efficiently synchronizes to a direct sequence spread spectrum signal, said signal being spread with a maximal length spreading code of length N at a transmitter, N being divisible by a plurality of prime factors, comprising:

means for receiving said signal;

means for digitizing said signal; and

means for correlating said spreading code with said signal by calculating a Fast Fourier transform with a predetermined number of computations, said predetermined number of computations being lower than a minimum number of calculations required to correlate another signal despread with another maximal length spreading code that is greater than or equal to 15 and divisible by a lesser number of prime factors than N.

60. A direct sequence spread spectrum receiver configured to efficiently synchronize to a direct sequence spread spectrum signal, said signal being spread with a maximal length spreading code of length N at a transmitter, N being divisible by a plurality of prime factors, comprising:

a front-end device for receiving said signal;

a digitizer device for digitizing said signal; and

a processing device for correlating said spreading code with said signal by calculating a Fast Fourier transform with a predetermined number of computations, said predetermined number of computations being lower than a minimum number of calculations required to correlate another signal despread with another maximal length spreading code that is greater than or equal to 15 and divisible by a lesser number of prime factors than N.

61. A direct sequence spread spectrum receiver that efficiently performs synchronization of a direct sequence spread spectrum signal, said signal being spread with a maximal length spreading code of length N at a transmitter, N being divisible by a plurality of prime factors, comprising the steps of:

means for receiving said signal;

means for digitizing said signal; and

means for correlating said spreading code with said signal by calculating a Fast Fourier transform with a predetermined number of computations, said predetermined number of computations being lower than a minimum number of calculations required to correlate another signal despread with another maximal length spreading code that is greater than or equal to 15 and divisible by a lesser number of prime factors than N.

62. A method for setting a pre-detection bandwidth in a digital direct sequence spread spectrum receiver, comprising the steps of:

receiving and digitizing a direct sequence spread spectrum signal and producing data samples;

despreading a data set having N data samples with a pseudorandom noise code, used at a transmitter to originally spread a data signal to form said direct sequence spread spectrum signal, where N coincides in number with another set of samples representative of a pseudorandom noise code;

decimating by parts another data set corresponding to a despread signal and producing M partial decimation summed samples, a ratio of N to M being an amount by which said another data set is decimated, said decimation ratio being proportional to a reduction in effective sample rate and pre-detection Nyquist bandwidth;

squaring respective of said M partial decimation summed samples and producing squared samples; and

combining said squared samples to respective of said partial decimation summed samples, wherein said pre-detection bandwidth being greater than or equal to a bandwidth of the data signal.

63. The method of claim 62, wherein said combining step comprises at least one of adding and averaging said squared samples.

64. The method of claim 62, wherein said decimating step comprises decimating by a decimation ratio that is either integer or rational.

65. A digital direct sequence spread spectrum receiver that sets a pre-detection bandwidth, comprising:

means for receiving and digitizing a direct sequence spread spectrum signal and producing data samples;

means for despreading a data set having N data samples with a pseudorandom noise code, used at a transmitter to originally spread a data signal to form said direct sequence spread spectrum signal, where N coincides in number with another set of samples representative of a pseudorandom noise code;

means for decimating by parts another data set corresponding to a despread signal and producing M partial decimation summed samples, a ratio of N to M being an amount by which said another data set is decimated, said decimation ratio being proportional to a reduction in effective sample rate and pre-detection Nyquist bandwidth;

means for squaring respective of said M partial decimation summed samples and producing squared samples; and

means for combining said squared samples to respective of said partial decimation summed samples, wherein said pre-detection bandwidth being greater than or equal to a bandwidth of the data signal.

66. A digital direct sequence spread spectrum receiver configured to set a pre-detection bandwidth, comprising:

a front-end device for receiving and digitizing a direct sequence spread spectrum signal and producing data samples;

a despeading device for despreading a data set having N data samples with a pseudorandom noise code, used at a transmitter to originally spread a data signal to form said direct sequence spread spectrum signal, where N coincides in number with another set of samples representative of a pseudorandom noise code;

a decimation device for decimating by parts another data set corresponding to a despread signal and producing M partial decimation summed samples, a ratio of N to M being an amount by which said another data set is decimated, said decimation ratio being proportional to a reduction in effective sample rate and pre-detection Nyquist bandwidth;

a squaring device for squaring respective of said M partial decimation summed samples and producing squared samples; and

a combining device for combining said squared samples to respective of said partial decimation summed samples, wherein said pre-detection bandwidth being greater than or equal to a bandwidth of the data signal.

67. A digital direct sequence spread spectrum receiver, comprising:

means for receiving and digitizing a direct sequence spread spectrum signal and producing data samples;

means for despreading a data set having N data samples with a pseudorandom noise code, used at a transmitter to originally spread a data signal to form said direct sequence spread spectrum signal, where N coincides in number with another set of samples representative of a pseudorandom noise code;

means for decimating by parts another data set corresponding to a despread signal and producing M partial decimation summed samples, a ratio of N to M being an amount by which said another data set is decimated, said decimation ratio being proportional to a reduction in effective sample rate and pre-detection Nyquist bandwidth;

means for squaring respective of said M partial decimation summed samples and producing squared samples; and

means for combining said squared samples to respective of said partial decimation summed samples, wherein said pre-detection Nyquist bandwidth being greater than or equal to a bandwidth of the data signal.

68. A method for communicating using a direct sequence spread spectrum signal having symbol rates which are a multiple of a pseudorandom noise code repetition rate, comprising the steps of:

aligning respective data symbols with the pseudorandom noise code;

forming the direct sequence spread spectrum signal by inverting corresponding portions of said PN code for a portion of said symbols having a first logic value and not inverting corresponding portions for the other symbols;

transmitting in a transmitter said direct sequence spread spectrum signal;

receiving and correlating the direct sequence spread spectrum signal, and obtaining a correlation result;

partitioning said correlation result to align with said portions that were inverted in said forming step;

identifying partial correlation sums for fractional symbol correlation; and

demodulating said data using said partial correlation sums.

69. The method of claim 68, wherein said forming step comprises forming a binary phase shift keyed signal by modulating data on said direct sequence spread spectrum signal using 180 degree phase inversion of the frequency reference and inverting said phase for multiple times through a PN code at rates which divide the PN code rate or a multiple thereof by integers.

70. The method of claim 68, wherein said forming step comprises forming an on-off keyed signal, and said transmitting step comprises transmitting with a power amplifier being on when said direct sequence spread spectrum signal is at a first level and turning said amplifier off when said direct sequence spread spectrum signal is at a second level.

71. A direct sequence spread spectrum transmitter system that transmits a direct sequence spread spectrum signal having symbol rates which are a multiple of a pseudorandom noise code repetition rate, comprising:

means for aligning respective data symbols with the pseudorandom noise code;

means for forming the direct sequence spread spectrum signal by inverting corresponding portions of said pseudorandom noise code for a portion of said symbols having a first logic value and not inverting corresponding portions for the other symbols;

means for transmitting in a transmitter said direct sequence spread spectrum signal;

means for receiving and correlating the direct sequence spread spectrum signal, and obtaining a correlation result;

means for partitioning said correlation result to align with said portions that were previously inverted;

means for identifying partial correlation sums for fractional symbol correlation; and

means for demodulating said data using said partial correlation sums.

72. A direct sequence spread spectrum transmitter system configured to communicate a direct sequence spread spectrum signal having symbol rates which are a multiple of a pseudorandom noise code repetition rate, comprising:

an alignment device for aligning respective data symbols with the pseudorandom noise code;

an inverter for forming the direct sequence spread spectrum signal by inverting corresponding portions of said PN code for a portion of said symbols having a first logic value and not inverting corresponding portions for the other symbols;

a transmit mechanism for transmitting said direct sequence spread spectrum signal;

a processor device for receiving and correlating the direct sequence spread spectrum signal, and obtaining a correlation result;

a partition device for partitioning said correlation result to align with said portions that were previously inverted;

a device for identifying partial correlation sums for fractional symbol correlation; and

a demodulation device for demodulating said data using said partial correlation sums.

73. A communications system that communicates using a direct sequence spread spectrum signal having symbol rates which are a multiple of a pseudorandom noise code repetition rate, comprising:

a transmitter, comprising,

means for aligning respective data symbols with the pseudorandom noise code,

means for forming the direct sequence spread spectrum signal by inverting corresponding portions of said PN code for a portion of said symbols having a first logic value and not inverting corresponding portions for the other symbols, and

means for transmitting in a transmitter said direct sequence spread spectrum signal; and

a receiver, comprising,

means for receiving and correlating the direct sequence spread spectrum signal, and obtaining a correlation result,

means for partitioning said correlation result to align with said portions that were inverted in said means for forming,

means for identifying partial correlation sums for fractional symbol correlation, and

means for demodulating said data using said partial correlation sums.

74. A method for implementing down conversion, channelization, and code filtering steps in a direct sequence spread spectrum receiver having a fast Fourier transform correlator, comprising the steps of:

applying one period of a spreading code at 4 samples/chip to a fast Fourier transform, said spreading code being used at a transmitter to form a direct sequence spread spectrum signal received by said receiver, said fast Fourier transform having output points;

filtering said output points in a rectangular filter having a bandwidth corresponding to a chip rate of said spreading code and retaining 1/4 of the output points centered on DC, and computing a complex conjugate of a filtered output and saving the complex conjugate as a filtered reference code;

maintaining a real-time counter for subsequent signal phase alignment;

sampling a received bandpass signal at 4 samples per chip for a duration of one code period, said bandpass signal having a center frequency approximately equal to a chip rate;

computing a fast Fourier transform of said bandpass signal and producing fast Fourier transform points;

downconverting said signal and channelizing a frequency uncertainty bandwidth by relabling 1/4 of said fast Fourier transform output points centered at a frequency corresponding to an intermediate frequency plus a channel offset frequency as points being centered at 0 Hz;

multiplying said relabled output points by said saved filtered reference code and obtaining an output data set;

performing a coarse search correlation operation in one chip steps in one channel by performing an inverse fast Fourier Transform on said output data set; and

repeating said downconverting, multiplying and performing step for the other channels.

75. The method of claim 74, further comprising the steps of:

implementing diversity reception by at least one of,

selecting an antenna from a plurality of antennas and performing said correlating step, and

selecting a center transmit frequency from a plurality of center transmit frequencies and performing said correlating step; and

repeating a respective one of said selecting an antenna step for the other antennas of said plurality of antennas and selecting a center transmit frequency step for the other center transmit frequencies, and coordinating respective of said selecting steps with a settling time associated with selecting an antenna and selecting a center frequency for a duration that is less than or equal to a duration of a correlation operation.

76. The method of claim 75, wherein said repeating step comprises cycling through predetermined frequency and antenna combinations.

77. A direct sequence spread spectrum receiver that implements down conversion, channelization, and code filtering, comprising:

means for applying one period of a spreading code at 4 samples/chip to a fast Fourier transform, said spreading code being used at a transmitter to form a direct sequence spread spectrum signal received by said receiver, said fast Fourier transform having output points;

means for filtering said output points in a rectangular filter having a bandwidth corresponding to a chip rate of said spreading code and retaining 1/4 of the output points centered on DC, and computing a complex conjugate of a filtered output and saving the complex conjugate as a filtered reference code;

means for maintaining a real-time counter for subsequent signal phase alignment;

means for sampling a received bandpass signal at 4 samples per chip for a duration of one code period, said bandpass signal having a center frequency approximately equal to a chip rate;

means for computing a fast Fourier transform of said bandpass signal and producing fast Fourier transform points;

means for downconverting said signal and channelizing a frequency uncertainty bandwidth by relabeling 1/4 of said fast Fourier transform output points centered at a frequency corresponding to an intermediate frequency plus a channel offset frequency as points being centered at 0 Hz;

means for multiplying said relabeled output points by said saved filtered reference code and obtaining an output data set;

means for performing a coarse search correlation operation in one chip steps in one channel by performing an inverse fast Fourier Transform on said output data set; and

means for repeating said downconverting, multiplying and performing step for the other channels.

78. A direct sequence spread spectrum receiver receiver configured to implement down conversion, channelization, and code filtering operations, comprising:

an application device for applying one period of a spreading code at 4 samples/chip to a fast Fourier transform, said spreading code being used at a transmitter to form a direct sequence spread spectrum signal received by said receiver, said fast Fourier transform having output points;

a filter for filtering said output points in a rectangular filter having a bandwidth corresponding, to a chip rate of said spreading code and retaining 1/4 of the output points centered on DC, and computing a complex conjugate of a filtered output and saving the complex conjugate as a filtered reference code;

a device for maintaining a real-time counter used for subsequent signal phase alignment;

a sampling device sampling a received band;

pass signal at 4 samples per chip for a duration of one code period, said bandpass signal having a center frequency approximately equal to a chip rate;

a processing device for computing a fast Fourier transform of said bandpass signal and producing fast Fourier transform points;

a downconversion device for downconverting said signal and channelizing a frequency uncertainty bandwidth by relabeling 1/4 of said fast Fourier transform output points centered at a frequency corresponding to an intermediate frequency plus a channel offset frequency as points being centered at 0 Hz;

a multiplication device for multiplying said relabeled output points by said saved filtered reference code and obtaining an output data set;

a signal processing device for performing a coarse search correlation operation in one chip steps in one channel by performing an inverse fast Fourier Transform on said output data set; and

a signal processing flow control device for repeating downconverting, multiplying and performing options for the other channels.

79. A direct sequence spread spectrum receiver, comprising:

means for calculating a fast Fourier transform;

means for applying one period of a spreading code at 4 samples/chip to the means for calculating the fast Fourier transform, said spreading code being used at a transmitter to form a direct sequence spread spectrum signal received by said receiver, said fast Fourier transform having output points;

means for filtering said output points in a rectangular filter having a bandwidth corresponding to a chip rate of said spreading code and retaining 1/4 of the output points centered on DC, and computing a complex conjugate of a filtered output and saving the complex conjugate as a filtered reference code;

means for maintaining a real-time counter for subsequent signal phase alignment;

means for sampling a received bandpass signal at 4 samples per chip for a duration of one code period, said bandpass signal having a center frequency approximately equal to a chip rate, said means for calculating a fast Fourier transform computing a fast Fourier transform of said bandpass signal and producing fast Fourier transform points;

means for downconverting said signal and channelizing a frequency uncertainty bandwidth by relabling 1/4 of said fast Fourier transform output points centered at a frequency corresponding to an intermediate frequency plus a channel offset frequency as points being centered at 0 Hz;

means for multiplying said relabled output points by said saved filtered reference code and obtaining an output data set;

means for performing a coarse search correlation operation in one chip steps in one channel by performing an inverse fast Fourier Transform on said output data set; and

means for repeatedly applying said means for downconverting, multiplying and performing for the other channels.

80. The receiver of claim 79, further comprising:

means for implementing diversity reception by at least one of,

means for selecting an antenna from a plurality of antennas and performing said correlating step, and

means for selecting a center transmit frequency from a plurality of center transmit frequencies and performing said correlating step; and

means for reapplying said means for selecting an antenna for the other antennas of said plurality of antennas and mean for selecting a center frequency for the other center transmit frequencies, and coordinating respective of said means for selecting with a settling time associated with selecting an antenna and selecting a center frequency for a duration that is less than or equal to a duration of a correlation operation.

81. A method for maximizing computational efficiency in a processor-based serial correlator in a direct sequence spread spectrum receiver, comprising the steps of:

sampling and storing as a signal data record of length N×

M a portion of a direct sequence spread spectrum signal, where N is a spreading code length and M is an integer ≧

1;

maintaining a real-time counter so that another sample of said direct sequence spread spectrum signal may be obtained at a later time, said real-time counter enabling said another sample to be taken a predetermined number of chip lengths after said sampling step was performed;

forming a coefficient data record of said spreading code, said coefficient data record having a length of N×

M;

sequentially computing correlation sums in said processor for at least a portion of all possible phase relationships of the sampled signal data record and the coefficient data record;

determining if one of said correlation sums exceeded a predetermined threshold indicative that a coarse search event has been detected; and

using said real-time counter to align at least said another sample with said coefficient record data if said coarse search event is detected, comprising the step of aligning said at least another sample with said coefficient record data based on a maximum correlation sum determined in said determining step.

82. The method of claim 81, wherein said sequentially computing step comprises sequentially computing correlation sums for all possible phase relationships of the sampled data record and the coefficient data record.

83. The method of claim 81 wherein said sampling step comprises sampling said data record of a direct sequence spread spectrum signal, where said direct sequence spread spectrum signal comprises a leader having a length being at least N+1, where N is for a combination of diversity options.

84. The method of claim 81, further comprising the step of turning off a radio front end of said receiver after said first sample is received and before said second sample is received.

85. The method of claim 81, wherein said determining step comprises the steps of:

determining a relative positional adjustment of the received signal with respect to the data coefficient data record corresponding to the spreading code and adjusting the data coefficient data record by the relative positional adjustment;

forming a mixed signal by mixing the received signal with the data coefficient data record after said adjusting step;

filtering the mixed signal with a lowpass filter to form a filtered signal;

measuring a power of the filtered signal and repeating said determining step, forming step and filtering step for each relative phase position between the received signal and the data coefficient data record;

determining which relative phase position provided a maximum power;

determining an average power over at least a portion of the all relative phase positions excluding phase positions where said the maximum power occurred and within one chip interval of where the maximum occurred; and

comparing the measured maximum with the average power and deciding that correlation was achieved to within 1 chip interval if said maximum power exceeds said average power by a predetermined amount.

86. The method of claim 81, wherein said determining step comprises the steps of:

determining a relative positional adjustment of the received signal with respect to the data coefficient data record corresponding to the spreading code and adjusting the data coefficient data record by the relative positional adjustment;

forming a mixed signal by mixing the received signal with the data coefficient data record after said adjusting step;

filtering the mixed signal with a plurality of adjacent filters, each having a bandwidth greater than or equal to a bandwidth of the signal after being despread, and forming a plurality of filtered signals;

measuring respective powers for the plurality of filtered signals and repeating said determining step, forming step, filtering step and measuring step for each relative phase position between the received signal and the data coefficient data record and for each of the adjacent filters;

determining which relative phase position provided a maximum power;

determining an average power over at least a portion of all relative phase positions except for the maximum and within one chip interval of the maximum; and

comparing the measured maximum with the average power and deciding that correlation was achieved to within 1 chip interval if said maximum power exceeds said average power by a predetermined amount.

87. The method of claim 81, wherein:

said sampling step comprising sampling with a sampled limiter; and

said determining step comprises the steps of,

determining a relative positional adjustment of the received signal with respect to the data coefficient data record corresponding to the spreading code and adjusting the data coefficient data record by the relative positional adjustment,

forming a mixed signal by mixing the received signal with the data coefficient data record after said adjusting step,

filtering the mixed signal with a plurality of adjacent filters, each having a bandwidth greater than or equal to a bandwidth of the signal after being despreads, and forming a plurality of filtered signals,

measuring respective powers for the plurality of filtered signals and repeating said determining step, forming step, filtering step and measuring step for each relative phase position between the received signal and the data coefficient data record and for each of the adjacent filters,

determining which relative phase position provided a maximum power, and

comparing the measured maximum with a predetermined value and deciding that correlation was achieved to within 1 chip interval if said maximum power exceeds said predetermined power by a predetermined amount.

88. The system of claim 81 wherein, said receiver further comprises:

a plurality of antennas;

a diversity reception control mechanism, comprising,

a selection mechanism for selecting one of said plurality of antennas after determining which of said antennas provides a signal the yields a correlation result meeting a selection threshold;

a frequency diversity determination mechanism configured to determine at which of a plurality of frequencies a transmitted signal is centered and receive the transmitted signal at the frequency after making the determination.

89. A direct sequence spread spectrum receiver comprising:

means for sampling and storing as a signal data record of length N×

M a portion of a direct sequence spread spectrum signal, where N is a spreading code length and M is an integer ≧

1;

means for maintaining a real-time counter so that another sample of said direct sequence spread spectrum signal may be obtained at a later time, said real-time counter enabling said another sample to be taken a predetermined number of chip lengths after sampling;

means for forming a coefficient data record of said spreading code, said coefficient data record having a length of N×

M;

means for sequentially computing correlation sums in said processor for at least a portion of all possible phase relationships of the sampled signal data record and the coefficient data record;

means for determining if one of said correlation sums exceeded a predetermined threshold indicative of a coarse search detection event; and

means for using said real-time counter to align at least said another sample with said coefficient data if said course search event is detected, comprising the means for aligning said at least another sample with said coefficient list based on a maximum correlation sum determined by said means for determining.

90. A direct sequence spread spectrum receiver comprising:

a device for sampling and storing as a signal data record of length N×

M a portion of a direct sequence spread spectrum signal, where N is a spreading code length and M is an integer ≧

1;

a device for maintaining a real-time counter so that another sample of said direct sequence spread spectrum signal may be obtained at a later time, said real-time counter enabling said another sample to be taken a predetermined number of chip lengths after sampling;

a formating device for forming a coefficient data record of said spreading code, said coefficient data record having a length of N×

M;

a correlation device for sequentially computing correlation sums in said processor for at least a portion of all possible phase relationships of the sampled signal data record and the coefficient data record;

a determination device for determining if one of said correlation sums exceeded a predetermined threshold indicative of a coarse search detection event; and

an alignment device for using said real-time counter to align at least said another sample with said coefficient data if said course search event is detected, and for aligning the at least another sample with said coefficient list based on a maximum correlation sum previously determined.

91. A direct sequence spread spectrum receiver, comprising:

means for sampling and storing as a signal data record of length N×

M a portion of a direct sequence spread spectrum signal, where N is a spreading code length and M is an integer ≧

1;

means for maintaining a real-time counter so that another sample of said direct sequence spread spectrum signal may be obtained at a later time, said real-time counter enabling said another sample to be taken a predetermined number of chip lengths after sampling by said means for sampling;

means for forming a coefficient data record of said spreading code, said coefficient data record having a length of N×

M;

means for sequentially computing correlation sums in said processor for at least a portion of all possible phase relationships of the sampled signal data record and the coefficient data record;

means for determining if one of said correlation sums exceeded a predetermined threshold indicative that a coarse search has been detected; and

means for using said real-time counter to align at least said another sample with said coefficient data if said coarse search event is detected, comprising means for aligning said at least another sample with said coefficient data record based on a maximum correlation sum determined in said means for determining.

92. A direct sequence spread spectrum system comprising:

a transmitter configured to transmit a direct sequence spread spectrum signal comprising,

a pseudorandom noise code generator that produces a pseudorandom spreading sequence having a predetermined length, and

a message formatting mechanism configured to form said direct sequence signal to have a leader component followed by a data pattern component, said leader component comprising plural copies of said pseudorandom spreading sequence and having a predetermined transmission length, said data pattern being spread by said pseudorandom spreading sequence; and

a receiver that receives said spread spectrum signal comprising,

a radio front-end that receives a first sample of said signal corresponding in length to at least one copy of said pseudorandom spreading sequence in said leader,

an acquisition mechanism configured to correlate said first sample with the pseudorandom sequence and determine whether a correlation value exceeds a predetermined threshold, indicative of coarse synchronization being achieved, said acquisition mechanism requiring a predetermined amount of processing time to correlate said first sample with said pseudorandom sequence and determine whether coarse synchronization has been achieved, said processing time being not greater than 1/2 the transmission length, wherein if said first sample includes a beginning of said leader but not including a full copy of said pseudorandom code, said receiver has enough time to receive a second sample of said signal and acquire coarse synchronization before said data is transmitted by transmitter.

93. The receiver of claim 92 wherein:

said pseudorandom noise code generator of said transmitter comprises means for producing the pseudorandom spreading sequence having a predetermined length;

said message formatting mechanism of said transmitter comprises means for forming said direct sequence message to have the leader component followed by the data pattern component; and

said acquisition mechanism comprises means to correlate said first sample with the pseudorandom sequence and determine whether a correlation value exceeds a predetermined threshold, indicative of coarse synchronization being achieved.

94. A direct sequence spread spectrum system comprising:

a transmitter comprising

means for generating a pseudorandom spreading sequence having a predetermined length, and

means for forming said direct sequence spread spectrum message to have a leader component followed by a data pattern component, said leader component comprising plural copies of said pseudorandom spreading sequence and having a predetermined transmission length, said data pattern being spread by said pseudorandom spreading sequence; and

a receiver comprising,

means for receiving a first sample of said signal corresponding in length to at least one copy of said pseudorandom spreading sequence in said leader,

means for correlating said first sample with the pseudorandom sequence and determining whether a correlation value exceeds a predetermined threshold, indicative of course synchronization being achieved, and for requiring a predetermined amount of processing time to correlate said first sample with said pseudorandom sequence and determine whether course synchronization has been achieved, said processing time being not greater than 1/2 the transmission length, wherein if said first sample includes a beginning of said leader but not including a full copy of said pseudorandom code, said receiver has enough time to receive a second sample of said signal and acquire course synchronization before said data is transmitted by transmitter.

95. A direct sequence spread spectrum system comprising:

a transmitter configured to transmit a direct sequence spread spectrum signal comprising,

a pseudorandom noise code generator that produces a pseudorandom spreading sequence having a predetermined length, and

a message formatting mechanism configured to form said direct sequence message to have a leader component followed by a data pattern component, said leader component comprising plural copies of said pseudorandom spreading sequence and having a predetermined transmission length, said data pattern being spread by said pseudorandom spreading sequence; and

a receiver that receives said spread spectrum signal comprising,

a radio front-end that receives a first sample of said signal corresponding in length to at least one copy of said pseudorandom spreading sequence in said leader,

an acquisition mechanism configured to correlate said first sample with the pseudorandom sequence and determine whether a correlation value exceeds a predetermined threshold, indicative of course synchronization being achieved, said acquisition mechanism requiring a predetermined amount of processing time to correlate said first sample with said pseudorandom sequence and determine whether course synchronization has been achieved, said processing time being not greater than 1/2 the transmission length, wherein if said first sample includes a beginning of said leader but not including a full copy of said pseudorandom code, said receiver has enough time to receive a second sample of said signal and acquire course synchronization before said data is transmitted by transmitter.

96. A direct sequence spread spectrum receiver that is adapted to conserve power when executing a serial search operation to determine if a sample of a received signal is aligned within a predetermined number of chip intervals relative to a spreading code produced in said receiver, said spreading code employed by a transmitter to spread a data signal and form the direct sequence spread spectrum signal, comprising:

a radio front end that acquires a first sample of said signal, said radio-front end comprising a digitizer that converts said sample into a digital signal;

a signal processor comprising,

a memory configured to hold said digital signal,

at least one of,

another memory configured to hold a copy of said spreading code, and

a spreading code generator,

a correlation mechanism that correlates said copy of the spreading code with said digital signal, and

a detection mechanism that detects if a correlation output signal from said correlation mechanism is greater than a predetermined amount so as to signify that said copy of said spreading code is aligned with said signal to within a predetermined chip interval, said chip interval corresponding to a chip of said spreading code; and

a controller configured to control when power is applied to said radio front end, said controller accounting for a predetermined amount of settling time prior to data acquisition, said controller applying power to the data acquisition section when acquiring said sample, removing power after said first sample is acquired and while said correlation mechanism and said detection mechanism are correlating said sample and determining whether said sample and said spreading code are aligned.

97. The receiver of claim 96, wherein said controller is configured to reapply power to the data acquisition section if said detection mechanism determines that said first sample did not correlate, and said data acquisition mechanism then acquires a second sample.

98. The receiver of claim 96, wherein said signal processing section includes a timer connected to said controller so that if correlation was achieved, the data acquisition section will acquire the other portion of the signal in alignment with the relative positional alignment of the first sample and the spreading code as determined by the correlation mechanism.

99. The receiver of claim 96, wherein said controller is also configured to control power to signal processing section.

100. The receiver of claim 96, wherein:

said digitizer comprises means for converting said sample into a digital signal;

said correlation mechanism comprises means for correlating said copy of the spreading code said digital signal;

said detection mechanism comprises means for detecting if the correlation output signal from said means for correlating is greater than a predetermined amount so as to signify that said copy of said spreading code is aligned with said signal to within a predetermined chip interval, said chip interval corresponding to a chip of said spreading code; and

said controller comprises means for controlling when power is applied to said radio front end, and for applying power to the data acquisition section when acquiring said sample, removing power after said first sample is acquired and while said means for correlating and said means for detecting are correlating said sample and determining whether said sample and said spreading code are aligned.

101. The receiver of claim 96, wherein at least one of said signal processor and said controller further comprise a computer-readable medium whose contents cause a processor to operate as at least one of said signal processor and said controller.

102. The receiver of claim 96 configured to perform a method comprising the steps of:

converting said sample into said digital signal;

correlating said copy of the spreading code with said digital signal;

detecting if the correlation output signal from said means for correlating is greater than a predetermined amount so as to signify that said copy of said spreading code is aligned with said signal to within a predetermined chip interval, said chip interval corresponding to a chip of said spreading code; and

controlling when power is applied to said radio front end, and for applying power to the data acquisition section when acquiring said sample, removing power after said first sample is acquired and while said means for correlating and said means for detecting are correlating said sample and determining whether said sample and said spreading code are aligned.

103. The receiver of claim 96, further comprising:

a combiner that combines one period of a spreading code at 4 samples/chip to a fast Fourier transform, said fast Fourier transform having output points;

a filter that filters output points in a rectangular filter having a bandwidth corresponding to a chip rate of said spreading code and retaining 1/4 of the output points centered at 0 Hz, and computing a complex conjugate of a filtered output and saving the complex conjugate as a filtered reference code;

a real-time counter for subsequent signal phase alignment;

an analog to digital converter that digitized a received bandpass signal at 4 samples per chip for a duration of one code period, said bandpass signal having a center frequency approximately equal to a chip rate;

a processor comprising,

a fast Fourier transform mechanism that transforms said bandpass signal and produces fast Fourier transform points,

a downconversion and channelization mechanism that downconverts said signal and channelizes a frequency uncertainty bandwidth by relabling 1/4 of said fast Fourier transform output points centered at a frequency corresponding to an intermediate frequency plus a channel offset frequency as points being centered at 0 Hz,

a multiplication mechanism configured to multiply said relabled output points by said saved filtered reference code and obtaining an output data set,

a coarse search correlation mechanism that performs a correlation operation on said output data set in one chip steps in one channel by performing an inverse fast Fourier Transform on said output data set; and

a repeating mechanisms that applies signals from other channels to said downconversion and channelization mechanism, multiplication mechanism and coarse search correlation mechanism for the other channels;

a low-power, continuous, state-independent clock configured to cause said receiver to enter an idle state so as to draw minimal power while in the idle state and to enter an active state where said receiver performs communication functions, said state-independent clock causing said active and idle states to be synchronized with external events.

104. The receiver of claim 103 further comprising a computer-readable medium whose contents cause said processor to implement said fast Fourier transform mechanism, down conversion and channelization mechanism, multiplication mechanism, coarse search correlation mechanism and repeating mechanisms.

105. The receiver of claim 103, further comprising:

a transmitter configured to transmit a signal and enable said receiver to perform transceive functions, said low-power, continuous, state-independent clock configured to cause said transmitter to enter an idle state so as to draw minimal power while in the idle state and to enter an active state where said transmitter performs communication functions, said state-independent clock causing said active and idle states to be synchronized with external events.

106. The receiver of claim 96, further comprising:

a sampling device and memory configured to sample and store as a signal data record of length N×

M a portion of a direct sequence spread spectrum signal, where N is a spreading code length and M is an integer ≧

1;

a real-time counter so that another sample of said direct sequence spread spectrum signal may be obtained at a later time, a predetermined number of chip lengths after said sampling step was performed;

a spreading code generator configured to form a coefficient data record of said spreading code, said coefficient data record having a length of N×

M;

a processor comprising,

a correlation mechanism that sequentially computes correlation sums for at least a portion of all possible phase relationships of the sampled signal data record and the coefficient data record and determining if one of said correlation sums exceeded a predetermined threshold indicative of a coarse search detection event;

an alignment mechanism configured to use said real-time counter to align at least said another sample with said coefficient data if said coarse search event is detected, and align said at least another sample with said coefficient list based on a maximum correlation sum determined in said correlation mechanism; and

a low-power, continuous, state-independent clock configured to cause said receiver and transmitter to enter an idle state so as to draw minimal power while in the idle state and to enter an active state where said transceiver performs communication functions, said state-independent clock causing said active and idle states to be synchronized with external events.

107. The receiver of claim 106 wherein said processor comprises a computer-readable medium whose contents causes said processor to implement at least one of said correlation mechanism, said alignment mechanism, and said low-power continuous, state-independent clock.

108. A direct sequence spread spectrum system configured to communicate data from a transmitter to a receiver in a direct sequence spread spectrum on-off-keyed system, comprising:

the transmitter, comprising a mechanism for enabling and disabling a spreading code used to spread the data signal and form the direct sequence spread spectrum on-off-keyed signal; and

the receiver comprising,

a receiver front-end configured to receive the direct sequence spread spectrum on-off-keyed signal,

a sampled limiter coupled to said receiver front-end and configured to produce a sampled signal corresponding to said direct sequence spread spectrum on-off-keyed signal,

a correlator that correlates said spreading code with said direct sequence spread spectrum on-off-keyed signal and produces a despread signal, said despread signal being represented as a correlation sum having partial sums, said partial sums corresponding to data elements of said data signal, and

a data demodulator that forms an output data stream of data elements, values of respective of said data elements corresponding to respective of said partial sums of said correlation sum.

109. The system of claim 108, wherein said transmitter further comprises:

an output signal port configured to couple the direct sequence spread spectrum on-off- keyed signal to a transmit antenna; and

an output power control mechanism configured to control a signal level of said direct sequence spread spectrum on-off-keyed signal, said power control mechanism adjusting said signal level to respective predetermined levels corresponding to respective portions of said signal corresponding to whether said spreading code was enabled or disabled for said respective portions, a difference between said predetermined levels being an amount that meets or exceeds a processing gain associated with said direct sequence spread spectrum on-off-keyed signal.

110. The system of claim 108, wherein said output power control mechanism further comprises means to encode the signal with a synchronization data so as to enable the spreading code to align thereto with no signal output attenuation, and not encoding with the synchronization data attenuates an output signal by at least a process gain of said signal.

111. The system of claim 108, wherein:

the transmitter further comprises,

a memory device coupled to a processing engine that controllably enables and disables the spreading code in the direct sequence spread spectrum on-off-keyed signal.

112. The system of claim 108, further comprising a computer-readable memory in said receiver whose contents causes a processor to implement said correlator.

113. The system of claim 108 configured to implement a method comprising the steps of enabling and disabling a spreading code used to spread the data signal and form the direct sequence spread spectrum on-off-keyed signal;

correlating in a receiver the spreading code with the direct sequence spread spectrum on-off-keyed signal and producing a despread signal; and

forming an output data stream of data elements, values of respective of said data elements corresponding to respective of said particular sums of said correlation sum.

114. The system of claim 108, wherein:

said mechanism for enabling and disabling comprises means for enabling and disabling a spreading code;

said receiver front-end comprising means for receiving the direct sequence spread spectrum on-off-keyed signal;

said sample limiter comprising means for producing a sampled signal;

said correlator comprising means for correlating said spreading code with said direct sequence spread spectrum on-off-keyed signal and producing a spreading signal, said spreading signal being represented as a correlation sum having partial sums; and

said data demodulator comprising means for forming an output data stream of data elements, values of respective of said data elements corresponding to respective of said partial sums of said correlation sum.

115. A direct sequence spread spectrum system for transmitting a direct sequence spread spectrum signal from a transmitter to a receiver, comprising:

the transmitter, said transmitter being configured to transmit the direct sequence spread spectrum signal in at least one of a plurality of frequencies, comprising,

a carrier frequency selection device configured to select said at least one of said plurality of transmitting frequencies,

a signal formatting mechanism configured to form said signal, said signal comprising a leader portion followed by a data portion, said leader comprising a code having a predetermined length, said code being repeated a plurality of times in said leader, a length of said leader being transmitted for a duration being at least twice as long as a maximum signal acquisition time required by the receiver to acquire the signal, said data portion being spread by said code; and

the receiver that receives said direct sequence spread spectrum signal, comprising,

a correlator configured to despread the spread spectrum signal and determine whether said direct sequence spread spectrum signal is present within said maximum signal acquisition time, wherein if said correlator attempts to acquire said transmitted signal based only on a fraction of a beginning portion of said leader, said leader being of sufficient length for said receiver to acquire the direct sequence spread spectrum signal by correlating a second portion of said leader, prior to said data portion of said direct sequence spread spectrum signal.

116. The system of claim 115, wherein:

said transmitter further comprises a computer-readable medium whose contents cause a processor to implement the signal formatting mechanism; and

said receiver further comprising a computer-readable medium whose contents cause a processor contained therein to implement said correlator.

117. The system of claim 115, wherein:

said signal formatting mechanism of said transmitter comprises means for forming said signal so as to have said leader portion followed by said data portion; and

said correlator of said receiver comprises means for despreading the spread spectrum signal and determining whether said direct sequence spread spectrum is present within said maximum signal acquisition time wherein if said correlator attempts to acquire said transmitted signal based only on a fraction of a beginning portion of said leader, said leader being of sufficient length for said receiver to acquire the direct sequence spread spectrum signal by correlating a second portion of said leader, prior to said data portion of said direct sequence spread spectrum signal.

118. The system of claim 115 configured to implement a process for transmitting and receiving said direct sequence spread spectrum signal comprising the steps of:

forming said signal so as to have a leader portion followed by a data portion, said leader portion comprising a code having a predetermined length, said code being repeated a plurality of times in said leader, a length of said leader being transmitted for a duration being at least twice as long as a maximum signal acquisition time required by the receiver to acquire the signal, said data portion being spread by said code; and

despreading in the receiver the spread spectrum signal and determining whether said direct sequence spread spectrum signal is present within said maximum signal acquisition time, wherein if said correlator attempts to acquire said transmitted signal based only on a fraction of said beginning portion of said leader, said leader being of sufficient length for said receiver to acquire the direct sequence spread spectrum signal by correlating a second portion of said leader, prior to said data portion of said direct sequence spread spectrum signal.

119. The system of claim 115, wherein said receiver further comprises:

a frequency diversity frequency selector that selects at least one of said frequencies for receiving said signal and determining whether said signal is acquired;

said correlator comprising,

a relative position adjustment mechanism that adjusts a phase of received signal with respect to a locally generated spreading signal,

a signal combiner configured to combine the spreading signal with the received signal and produce a mixed signal,

a filter that limits a bandwidth of said mixed signal,

a power measuring device that measures a power of said mixed signal for respective of phases adjusted by said relative position adjustment mechanism, and that determines a maximum power,

an averaging device that determines an average power for each phase position adjusted by said relative position adjustment mechanism, said average power excluding said maximum power and powers measured within one code chip interval of said maximum, and

a comparator that compares said maximum with said average power and determines whether acquisition is achieved for the phase position corresponding with said maximum if said maximum exceeds said average by a predetermined amount.

120. receiver of claim 119 wherein:

said correlator is configured to determine whether acquisition is achieved for all frequencies selected by said frequency selector.

121. The system of claim 115, wherein said receiver further comprises:

a plurality of antennas;

a diversity reception control mechanism, comprising,

a relative position adjustment mechanism that adjusts a phase of a received signal from one of said plurality of antennas with respect to a locally generated spreading signal,

a signal combiner configured to combine the spreading signal with the signal received and produce a mixed signal,

a filter that limits a bandwidth of said mixed signal,

a power measuring device that measures a power of said mixed signal and for respective phases adjusted by said relative position adjustment mechanism, and that determines a maximum power for said mixed signal,

an averaging device that determines an average power for each phase position adjusted by said relative position adjustment mechanism, said average power excluding said maximum power and powers measured within one code chip of said maximum,

a comparator that compares said maximum with said average power and determines whether acquisition is achieved for the phase position corresponding with said maximum if said maximum exceeds said average by a predetermined amount, and

a selection mechanism for selecting in a predetermined order respective of said plurality of antennas, said selection mechanism coupling an output of a selected antenna to said signal combiner for processing in said signal combiner, filter, power measuring device, averaging device and comparator.

122. A direct sequence spread spectrum communications system comprising:

a transmitter that transmits a direct sequence spread spectrum signal formed by spreading a data signal with a pseudorandom code, said transmitter including a frequency reference that imparts a frequency uncertainty in said direct sequence spread spectrum signal due to a suboptimal frequency accuracy; and

a receiver that receives said direct sequence spread spectrum signal, comprising,

a timer configured to measure a length of time between when a portion of the direct sequence spread spectrum signal is received and when the receiver determines in a correlation mechanism that the direct sequence spread spectrum signal is acquired so that another portion of the direct sequence spread spectrum signal will be compared in phase with a despreading code used in the correlation mechanism,

the correlation mechanism which is configured to determine a cross correlation of the portion of the signal with the pseudorandom code so as to form a cross correlation result in a magnitude array, said pseudorandom code represented by a coefficient data record,

a memory configured to hold said magnitude array,

a signal acquisition section that uses said timer to acquire another portion of said direct sequence spread spectrum signal to be coincident with the despreading code for cross correlation in said correlation mechanism with the coefficient data record used for the portion of the signal and for producing subsequent magnitude arrays,

an averaging mechanism configured to average the magnitude array with the subsequent magnitude arrays to form an average array; and

an acquisition detection mechanism that determines if entries in said average array indicate that signal acquisition is achieved.

123. The system of claim 122, further comprising a computer-readable medium whose contents cause a processor to implement at least one of said timer, correlation mechanism, averaging mechanism, and acquisition detection mechanism.

124. The system of claim 122, wherein:

said timer of said receiver comprises means for measuring a length of time;

said correlation mechanism of said receiver comprises means for determining a cross correlation of the portion of the signal with the pseudorandom code;

said signal acquisition section comprises means for acquiring said another portion of said direct sequence spread spectrum signal to be coincident with the spreading code;

said averaging mechanism comprises means for averaging the magnitude array with the subsequent magnitude arrays to form the average array; and

said acquisition detection mechanism comprises means for determining if entries in said average array indicate that signal acquisition is achieved.

125. A method for transmitting a direct sequence spread spectrum signal comprising the steps of:

transmitting a direct sequence spread spectrum signal formed by spreading a data signal with a pseudorandom code, said transmitter including a frequency reference that imparts a frequency uncertainty in said direct sequence spread spectrum signal due to a suboptimal frequency accuracy; and

receiving said direct sequence spread spectrum signal, comprising,

measuring a length of time between when a portion of the direct sequence spread spectrum signal is received and when the receiver determines in a correlation mechanism that the direct sequence spread spectrum signal is acquired so that another portion of the direct sequence spread spectrum signal will be compared in phase with a despreading code used in the correlation mechanism,

determining a cross correlation of the portion of the signal with the pseudorandom code so as to form a cross correlation result in a magnitude array, said pseudorandom code represented by a coefficient data record,

storing said magnitude array in a memory,

acquiring another portion of said direct sequence spread spectrum signal,

measuring a time span with a timer so that said another portion of said direct sequence spread spectrum signal will be coincident with the despreading code for cross correlation in said correlation mechanism with the coefficient data record used for the portion of the signal and for producing subsequent magnitude arrays,

averaging the magnitude array with the subsequent magnitude arrays to form an average magnitude array, and

determining if entries in said average magnitude array indicate that signal acquisition is achieved.

126. A direct sequence spread spectrum communications system comprising:

a transmitter that transmits a direct sequence spread spectrum signal formed by spreading a data signal with a pseudorandom code, said transmitter including a frequency reference that imparts a frequency uncertainty in said direct sequence spread spectrum signal due to a suboptimal frequency accuracy; and

a receiver that receives said direct sequence spread spectrum signal, comprising,

a timer configured to measure a length of time between when a portion of the direct sequence spread spectrum signal is received and when the receiver determines in a correlation mechanism that the direct sequence spread spectrum signal is acquired so that another portion of the direct sequence spread spectrum signal will be acquired so as to be aligned in phase with a despreading code used in the correlation mechanism,

the correlation mechanism which is configured to determine a cross correlation of the portion of the signal with the pseudorandom code and frequency plane so as to form a cross correlation result in a magnitude plane, said pseudorandom code represented by a coefficient data record,

a memory configured to hold said magnitude plane,

a signal acquisition section that uses said timer to acquire another portion of said direct sequence spread spectrum signal to be coincident with the despreading code for cross correlation in said correlation mechanism with the coefficient data record used for the portion of the signal and for producing subsequent magnitude planes,

an averaging mechanism configured to average the magnitude plane with the subsequent magnitude planes to form an average magnitude plane; and

an acquisition detection mechanism configured to determine if entries in said average magnitude plane indicate that signal acquisition is achieved.

127. The system of claim 126, further comprising a computer-readable medium whose contents cause a processor to implement at least one of said timer, correlation mechanism, averaging mechanism, and acquisition detection mechanism.

128. The system of claim 126, wherein:

said transmitter comprises means for forming said direct sequence spread spectrum signal;

said timer or said receiver comprise means for measuring the length of time;

the correlation mechanism comprises means for determining said cross correlation;

said signal acquisition section of said receiver comprises means for using said timer to acquire said another portion of said direct sequence spread spectrum signal;

said averaging mechanism comprises means for averaging the magnitude plane with the subsequent magnitude planes to form said average magnitude planes; and

said acquisition detection mechanism comprises means for determining if entries in said average magnitude plane indicate that signal acquisition is achieved.

129. A method for transmitting a direct sequence spread spectrum signal comprising the steps of:

transmitting a direct sequence spread spectrum signal formed by spreading a data signal with a pseudorandom code, said transmitter including a frequency reference that imparts a frequency uncertainty in said direct sequence spread spectrum signal due to a suboptimal frequency accuracy; and

receiving said direct sequence spread spectrum signal, comprising,

measuring a length of time between when a portion of the direct sequence spread spectrum signal is received and when the receiver determines in a correlation mechanism that the direct sequence spread spectrum signal is acquired so that another portion of the direct sequence spread spectrum signal will be compared in phase with a despreading code used in the correlation mechanism,

determining a cross correlation of the portion of the signal with the pseudorandom code so as to form a cross correlation result in a magnitude plane, said pseudorandom code represented by a coefficient data record,

storing said magnitude plane in a memory, acquiring another portion of said direct sequence spread spectrum signal,

measuring an elapsed time frame with a timer so that said another portion of said direct sequence spread spectrum signal will be coincident with the despreading code for cross correlation in said correlation mechanism with the coefficient data record used for the portion of the signal and for producing subsequent magnitude planes,

averaging the magnitude plane with the subsequent magnitude planes to form an average magnitude plane; and

determining if entries in said average magnitude plane indicate that signal acquisition is achieved.

130. A transmitter in a direct sequence spread spectrum communication system having frequency diversity, comprising:

a signal combiner that combines a data signal with a pseudorandom code that spreads the data signal into the direct sequence spread spectrum signal, said pseudorandom code comprising chips having a duration corresponding to a predetermined chipping rate;

a clock generator that generates a clock signal at a frequency that is a multiple of the chipping rate, said multiple being greater than or equal to 1, wherein

said combiner being configured to mix the direct sequence spread spectrum signal with said clock signal to produce a composite signal having two components centered at respective center frequencies that are separated by two times said clock frequency, said composite signal being transmitted to a direct sequence spread spectrum receiver that is configured to receive the composite signal and extract the data signal therefrom.

131. The transmitter of claim 130 further comprising a computer-readable medium whose contents cause a processor to implement said signal combiner.

132. The transmitter of claim 130, wherein:

said signal combiner comprises means for combining the data signal with the pseudorandom code;

said clock generator comprises means for generating the clock signal at the frequency that is the multiple of the chipping rate, said multiple being greater than or equal to 1; and

wherein,

said means for combining comprises means for mixing the direct sequence spread spectrum signal with the clock signal to produce the composite signal.

133. A method for transmitting in a direct sequence spread spectrum communication system, comprising the steps of:

combining a data signal with a pseudorandom code that spreads the data signal into the direct sequence spread spectrum signal, said pseudorandom code comprising chips having a duration corresponding to a predetermined chipping rate;

generating a clock signal at a frequency that is a multiple of the chipping rate, said multiple being greater than or equal to 1, wherein

mixing the direct sequence spread spectrum signal with said clock signal to produce a composite signal having two components centered at respective center frequencies that are separated by two times said clock frequency said composite signal being transmitted to a direct sequence spread spectrum receiver that is configured to receive the composite signal and extract the data signal therefrom.

134. A direct sequence spread spectrum system comprising:

a transmitter configured to transmit a direct sequence spread spectrum signal, comprising,

a transmitter frequency reference that produces a frequency with a predetermined accuracy,

a spreading code generator that receives said frequency from said transmitter frequency reference and generates said spreading code with a predetermined transmit signal chipping frequency error, said spreading code generator configured to produce a spread data signal by modulating a data signal with said spreading code, said spread data signal having a frequency error component attributable to said predetermined accuracy of the frequency,

a radio frequency generator configured to produce a radio frequency signal derived from said frequency from said transmitter frequency reference, said radio frequency signal having a frequency error attributable to said predetermined accuracy of said frequency, and

a transmitter signal combiner having a signal input connector configured to receive and combine said radio frequency signal and said spread data signal to produce the direct sequence spread spectrum signal; and

a receiver configured to extract said data signal from said direct sequence spread spectrum signal sent from said transmitter, comprising,

a frequency downconversion mechanism to lower a frequency of said direct sequence spread spectrum signal,

a spreading code generator configured to generate said spreading code,

a local time reference that controls said frequency downconversion mechanism and said spreading code generator;

a correlator that determines said frequency error by correlating said direct sequence spread spectrum signal with said spreading code,

a code phase prediction mechanism that predicts a drift in a phase of said spreading code relative to said direct sequence spread spectrum signal over a predetermined period of time, and

a code phase adjustment mechanism configured to adjust the phase of said spreading code to compensate for the drift in phase predicted in said code phase prediction mechanism, the adjusting mechanism adjusting said phase by fractional chip steps while simultaneously receiving and demodulating the direct sequence spread spectrum signal.

135. The system of claim 134, wherein said receiver comprises a multichannel receiver and said code phase prediction mechanism comprises a mechanism for using a channel index in which said signal is received as the predicted phase drift.

136. The system of claim 134, further comprising:

a receiver frequency reference that produces a frequency with another predetermined accuracy,

a code generator being coupled to the receiver frequency reference and configured to generate said spreading code, said spreading code having a chipping frequency error component, and

a receiver radio frequenty generator configured to produce a downconversion signal derived from frequency said receiver frequency reference, said downconversion signal having a frequency error attributable to said predetermined accuracy of said frequency from said receiver frequency reference.

137. The system of claim 136, further comprising:

means for using said prediction value to modify the code phase of its local code generator at specific points during a received message to maintain chip phase alignment between transmitter and receiver.

138. The system of claim 134, further comprising a computer-readable medium whose contents cause a processor to implement in said receiver at least one of said frequency down conversion mechanism, said correlator, said code phase prediction mechanism, and said code phase adjustment mechanism.

139. The system of claim 134, wherein:

said frequency downconversion mechanism comprises means for lowering a frequency of the direct sequence spread spectrum signal;

said spreading code generator comprises means for generating said spreading code;

said correlator comprises means for determining said frequency error;

said code phase prediction mechanism comprises means for predicting said drift; and

said code phase adjust mechanism comprises means for adjusting in fractional chip steps said phase so as to compensate for the drift in phase.

140. A method for communicating a direct sequence spread spectrum signal, comprising the steps of:

transmitting from a transmitter a direct sequence spread spectrum signal, comprising,

generating a transmitter frequency reference with a predetermined accuracy,

generating a transmitter spreading code that uses said transmitter frequency, reference with a predetermined transmit signal chipping frequency error, said spreading code configured to produce a spread data signal by modulating a data signal with said spreading code, said spread data signal having a frequency error component attributable to said predetermined accuracy of the frequency,

generating a radio frequency signal derived from said transmitter frequency reference, said radio frequency signal having a frequency error attributable to said predetermined accuracy of said frequency, and

combining said radio frequency signal and said spread data signal to produce the direct sequence spread spectrum signal; and

receiving said energy with a receiver configured to extract said data signal from said direct sequence spread spectrum signal transmitted from said transmitter, comprising,

receiving the direct sequence spread spectrum signal,

generating a receiver frequency reference with a predetermined accuracy,

downconverting the direct sequence spread spectrum signal to produce a reduced frequency direct sequence spread spectrum signal, said downconverting step having a frequency component based on said receiver frequency reference,

generating a receiver spreading code that uses said receiver frequency reference, said receiver spreading code producing a narrowband data signal by mixing said reduced frequency data signal with said spreading code, said narrowband data signal having a frequency error component attributable to said predetermined accuracy of the receiver frequency reference,

determining the frequency of the received direct sequence spread spectrum signal,

determining the frequency difference between the transmitter frequency reference and the receiver frequency reference,

predicting a drift in a phase of said receiver spreading code relative to said received direct sequence spread spectrum signal over a predetermined period of time, and

adjusting the phase of said receiver spreading code to compensate for the drift in phase predicted in said code phase predicting step, the adjusting step adjusting said phase by fractional chip steps while simultaneously receiving and demodulating the direct sequence spread spectrum signal.

141. A direct sequence spread spectrum communication network comprising:

a transmitter that transmits a direct sequence spread spectrum signal comprising a message;

a processor;

a plurality of receivers connected to one another in a multi-drop network, said processor being connected to the multi-drop network, respective of said receivers comprising a memory, wherein

respective of said receivers that receive said direct sequence spread spectrum signal store the message in said memory, said message having a unique identification,

respective of said receivers being configured to relay said message to said processor over the multi-drop network according to a signaling protocol, wherein

respective of the receivers monitor the multi-drop network for other message traffic and, if message traffic is present, determine if an identification of said message traffic is common with said message stored in said memory, and if said identification is common, eliminating the message in the memory because it is redundant with the message traffic being sent to the processor.

142. The network of claim 141, wherein said receivers further comprise a computer-readable medium whose contents cause a processor to implement the process for monitoring the multi-drop network, and determining if the identification of the message traffic in common with the message stored in memory if the message traffic is present, and if said identification is common, eliminating the message in the memory.

143. The network of claim 141, wherein:

respective of said receivers comprise means for relaying said message to said processor over the multi-drop network;

respective of said receivers comprise means for monitoring the multi-drop network for other message traffic;

respective of said receivers comprise means for determining an identification of said message traffic in common with said message stored in memory if said message traffic is present; and

respective of said receivers comprise means for eliminating the message in the memory if said identification is common.

144. A method for reducing message traffic on a multi-drop network comprising the steps of:

transmitting a direct sequence spread spectrum signal comprising a message from a transmitter, said message having a unique identification;

receiving said signal by at least one of a plurality of receivers connected to one another in the multi-drop network, said multi-drop network have a processor connected thereto, respective of said receivers comprising a memory;

relaying the message to said processor over the multi-drop network according to a signaling protocol;

storing said message of said direct sequence spread spectrum signal in said memory; and

monitoring with respective of the receivers communications in the multi-drop network for other message traffic and, if the other message traffic is present, determining if an identification of said message traffic is common with said message stored in said memory, and if said identification is common, eliminating the message in the memory because the message is redundant with the message traffic being sent to the processor.