Transition-controlled digital encoding and signal transmission system

• US 5,999,571 A
• Filed: 10/05/1995
• Issued: 12/07/1999
• Est. Priority Date: 10/05/1995
• Status: Expired due to Term

• Current Assignee: Nexus Display Technologies LLC (Acacia Research Corporation)
• Original Assignee: Silicon Image, Inc. (Lattice Semiconductor Corporation)
• Inventors: Shin, Yeshik, Kim, Sungjoon, Lee, David, Lee, Kyeongho
• Primary Examiner(s): Pham, Chi H.
• Assistant Examiner(s): Tran, Khai
• Application Number:
  US08/539,816
• Time in Patent Office: 1,524 Days
• Field of Search: 375/360, 375/364, 375/365, 375/366, 375/368, 375/292, 370/503, 370/509, 370/513, 370/514, 370/433, 370/463
• US Class Current: 375/292
• CPC Class Codes: H04L 2007/045 Fill bit or bits, idle words
• CPC Class Codes: H04L 25/03866 using scrambling
• CPC Class Codes: H04L 25/085 Arrangements for reducing interference in line transmission systems, e.g. by differential transmission
• CPC Class Codes: H04L 25/4915 using pattern inversion or substitution H04L25/4908 takes precedence
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04N 21/23602 Multiplexing isochronously with the video sync, e.g. according to bit-parallel or bit-serial interface formats, as SDI
• CPC Class Codes: H04N 21/4305 Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/4342 Demultiplexing isochronously with video sync, e.g. according to bit-parallel or bit-serial interface formats, as SDI
• CPC Class Codes: H04N 7/083 with signal insertion during the vertical and the horizontal blanking interval , e.g. MAC data signals
• CPC Class Codes: H04N 7/52 Systems for transmission of a pulse code modulated video signal with one or more other pulse code modulated signals, e.g. an audio signal or a synchronizing signal assembling of a multiplex stream by combining a video stream with other content or additional data, remultiplexing of multiplex streams, insertion of stuffing bits into the multiplex stream, assembling of a packetised elementary stream at server side H04N21/236; disassembling of a multiplex stream, remultiplexing of multiplex streams, extraction or processing of Service Information, disassembling of packetised elementary stream at client side H04N21/434

Abstract

A method and apparatus for producing a transition-controlled, DC-balanced sequence of characters from an input sequence of data bytes is disclosed herein. The bits in each of the data bytes are selectively complemented in accordance with the number of logical transitions in each data byte in order to produce selectively complemented data blocks. A cumulative disparity is then determined between the logical values of different type included within ones of the selectively complemented data blocks previously encoded into characters. In addition, a current disparity in a candidate character associated with a current one of the selectively complemented data blocks being encoded is also determined. The candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of a polarity opposite to a first polarity of the cumulative disparity. Alternately, the complement of the candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of the first polarity. In a high-transition mode of operation, the bits within data blocks including less than a minimum number of logical transitions are selectively complemented so that each such selectively complemented data block includes in excess of the minimum number of logical transitions. In a low-transition mode of operation, the bits within data blocks having more than a predefined number of logical transitions are selectively complemented so that each such selectively complemented data block includes less than the maximum number of logical transitions.

Claims

1. A system for detecting a boundary of a synchronization character within an encoded serial data stream including at least three repetitions of said synchronization character, said synchronization character having a number of logical transitions within a predetermined range, said system comprising:

means for coupling an input set of bits from said encoded serial data stream into a register;

means for performing a first set of logical operations at least upon adjacent ones of a first subset of said input set of bits and for grouping the results of said predefined logical operations into a set of groups;

means for comparing said groups in order to determine if said input set of bits corresponds to said at least three repetitions of said synchronization character;

detection logic means for identifying said boundary of said synchronization character on the basis of results of performance of a second set of logical operations upon said input set of bits; and

wherein said means for comparing includes means for comparing first and third of said groups and for comparing second and fourth of said groups, said input set of bits corresponding to said at least three repetitions of said synchronization character if said first group is equivalent to said third group and if said second group is equivalent to said fourth group.

2. A system for detecting a boundary of a synchronization character within an encoded serial data stream including at least three repetitions of said synchronization character, said synchronization character having a number of logical transitions within a predetermined range, said system comprising:

means for coupling an input set of bits from said encoded serial data stream into a register;

means for performing a first set of logical operations at least upon adjacent ones of a first subset of said input set of bits and for grouping the results of said predefined logical operations into a set of groups;

means for comparing said groups in order to determine if said input set of bits corresponds to said at least three repetitions of said synchronization character;

detection logic means for identifying said boundary of said synchronization character on the basis of results of performance of a second set of logical operations upon said input set of bits; and

wherein each of said repetitions of said synchronization character includes 10 bits, said means for grouping including means for forming four of said groups from said first subset of said input set of bits wherein said first subset is comprised of less than 22 bits.

3. A method for detecting a boundary of a synchronization character within an encoded serial data stream including at least three repetitions of said synchronization character, said synchronization character having a number of logical transitions within a predetermined range, said method comprising the steps of:

coupling an input set of bits from said encoded serial data stream into a register;

performing a first set of logical operations at least upon adjacent ones of a first subset of said input set of bits and for grouping the results of said predefined logical operations into a set of groups;

comparing said groups in order to determine if said input set of bits corresponds to said at least three repetitions of said synchronization character;

identifying said boundary of said synchronization character on the basis of results of performance of a second set of logical operations upon said input set of bits; and

wherein said step of comparing includes the step of comparing first and third of said groups and for comparing second and fourth of said groups, said input set of bits corresponding to said at least three repetitions of said synchronization character if said first group is equivalent to said third group and if said second group is equivalent to said fourth group.

4. A method for detecting a boundary of a synchronization character within an encoded serial data stream including at least three repetitions of said synchronization character, said synchronization character having a number of logical transitions within a predetermined range, said method comprising the steps of:

coupling an input set of bits from said encoded serial data stream into a register;

performing a first set of logical operations at least upon adjacent ones of a first subset of said input set of bits and for grouping the results of said predefined logical operations into a set of groups;

comparing said groups in order to determine if said input set of bits corresponds to said at least three repetitions of said synchronization character;

identifying said boundary of said synchronization character on the basis of results of performance of a second set of logical operations upon said input set of bits; and

wherein each of said repetitions of said synchronization character includes 10 bits, said step of grouping including the step of forming four of said groups from said first subset of said input set of bits wherein said first subset if comprised of less than 22 bits.