Circuit delay optimizing using circuit arrangement, layout information, and wiring delay information

• US 5,999,715 A
• Filed: 03/28/1997
• Issued: 12/07/1999
• Est. Priority Date: 09/29/1995
• Status: Expired due to Fees

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Sato, Koichi
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Siek, Vuthe
• Application Number:
  US08/825,399
• Time in Patent Office: 984 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 395/500.06, 395/500.11
• US Class Current: 716/113
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist

Abstract

A circuit delay optimizing apparatus, includes an information input unit with a logic synthesizer unit that receives, from a layout unit, layout information after completion of layout of a circuit to be changed and wiring and wiring delay information represented by wiring capacitances and fan-out numbers of individual wiring lines. A circuit change portion searching unit searches the layout information to determine a circuit change on the basis of the wiring delay information. Wiring delay information after a circuit change is determined with respect to the change portion of the circuit, through a predetermined technique. A wiring capacitance after the circuit change is calculated by using a function of a fan-out number after the circuit change, a fan-out number before the circuit change and a wiring capacitance before the circuit change. A wiring delay time is calculated from the calculated wiring capacitance by using a predetermined function and the calculated delay time is used to determine if it is an improvement over the delay time before the circuit change. A circuit changing unit changes the circuit change portion only after an improvement is determined.

Claims

1. A circuit delay optimizing method comprising the steps of:

inputting layout information, obtained after completion of layout of a circuit to be changed, and wiring and wiring delay information represented by wiring capacitances and fan-out numbers which are factors for determining delay times of individual wiring lines;

searching the layout information to determine a circuit change portion at which the circuit must be changed on the basis of the wiring delay information;

determining wiring delay information after a circuit change, which is obtained when said circuit change portion is changed, through a predetermined technique;

calculating a wiring capacitance after the circuit change by using a function of a fan-out number after the circuit change, a fan-out number before the circuit change and a wiring capacitance before the circuit change;

calculating a wiring delay time from the calculated wiring capacitance by using a predetermined function;

deciding whether the calculated delay time is an improvement over the delay time before the circuit change; and

changing the circuit change portion only after an improvement is determined in said deciding step.

2. A circuit delay optimizing method according to claim 1, wherein in said circuit change portion searching step, the circuit change portion is determined by deciding whether delay times of individual wiring lines at said circuit change portion are larger than an expected value.

3. A circuit delay optimizing method comprising the steps of:

inputting layout information, obtained after completion of arrangement of a circuit to be changed, including wiring and wiring delay information represented by wiring capacitances and fan-out numbers which are factors for determining delay times of individual wiring lines;

searching the layout information to determine a circuit change portion at which the circuit must be changed on the basis of the wiring delay information;

determining wiring delay information after a circuit change, which is obtained when said circuit change portion is changed, through a predetermined technique;

calculating a wiring capacitance after the circuit change by using a function of a fan-out number after the circuit change, a fan-out number before the circuit change and a wiring capacitance before the circuit change;

calculating a wiring delay time from the calculated wiring capacitance by using a predetermined function;

deciding whether the calculated delay time is an improvement over the delay time before the circuit change; and

changing the circuit change portion only after an improvement is determined in said deciding step,

wherein said function for calculating a wiring capacitance after the circuit change is a multiplication of a ratio of the fan-out number before the circuit change to the fan-out number after the circuit change by the wiring capacitance before the circuit change.

4. A circuit delay optimizing method according to claim 3, wherein the fan-out number after the circuit change is subtracted by one.

5. A circuit delay optimizing apparatus comprising:

an information input unit having a logic synthesizer unit and receiving, from a layout unit, layout information after completion of layout of a circuit to be changed and wiring and wiring delay information represented by wiring capacitances and fan-out number which are factors for determining delay times of individual wiring lines, said layout information and wiring delay information being supplied to said logic synthesizer unit;

a circuit change portion searching unit that searches said layout information to determine a circuit change portion, at which said circuit must be changed, on the basis of the wiring delay information;

a wiring delay information calculating unit that calculates wiring delay information after a circuit change, when the circuit change is effected with respect to the circuit change portion, through a predetermined technique;

a wiring delay estimating unit that calculates a wiring capacitance after the circuit change by using a function of a fan-out number after the circuit change, a fan-out number before the circuit change and a wiring capacitance before the circuit change;

a wiring delay improvement deciding unit that determines a wiring delay time from the calculated wiring capacitance by using a predetermined function and deciding whether the calculated delay time is an improvement over the delay time before the circuit change; and

a circuit changing unit that causes said logic synthesizer unit to change said circuit change portion only after an improvement is determined by said wiring delay improvement deciding unit.

6. The circuit delay optimizing apparatus according to claim 5, wherein the fan-out number after the circuit change is subtracted by one.

7. The circuit delay optimizing apparatus according to claim 5, wherein said circuit change portion searching unit determines the circuit change portion by deciding whether delay times of individual wiring lines are larger than an expected value.

8. A circuit delay optimizing apparatus according to claim 5, wherein said function that calculates the wiring capacitance after the circuit change is a multiplication of a ratio of the fan-out number before the circuit change to the fan-out number after the circuit change by the wiring capacitance before the circuit change.