Method and apparatus tracing any node of an emulation

• US 5,999,725 A
• Filed: 04/17/1998
• Issued: 12/07/1999
• Est. Priority Date: 04/23/1996
• Status: Expired due to Term

• Current Assignee: Mentor Graphics Corporation (Siemens AG), Mentor Graphics Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Reblewski, Frederic, Barbier, Jean, Lepape, Olivier
• Primary Examiner(s): Stamber, Eric W.
• Assistant Examiner(s): Knox, Lonnie A.
• Application Number:
  US09/062,240
• Time in Patent Office: 599 Days
• Field of Search: 364/500, 364/489, 364/490, 364/491, 364/578, 395/23
• US Class Current: 703/28
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation

Abstract

A method and apparatus for tracing any node in an emulator, including hidden nodes of a circuit design, includes maintaining a correspondence between physically observable nodes and hidden nodes of the circuit design being emulated. The correspondence identifies how values of the hidden nodes are to be determined based on corresponding ones of the physically observable nodes. The value of a hidden node is determined by obtaining the values of the corresponding physically observable nodes and identifying the value of the hidden node based on the correspondence between the corresponding physically observable nodes and the hidden node.

Claims

1. In an emulation system, a method for tracing a first plurality of nodes of a circuit design, the method comprising:

(a) maintaining relationships between a second plurality of nodes of the circuit design and the first plurality of nodes, including how values of the first plurality of nodes are to be determined based on the second plurality of nodes;

(b) accessing values of the second plurality of nodes; and

(c) determining the values of the first plurality of nodes based at least in part on both the values of the second plurality of nodes and the relationships between the second plurality of nodes and the first plurality of nodes.

2. The method of claim 1, wherein the maintaining operation of (a) comprises:

generating a first list listing the second plurality of nodes; and

generating a second list listing the first plurality of nodes, wherein each node of the second list is defined in terms of selected ones of the second plurality of nodes.

3. The method of claim 2, wherein the maintaining operation of (a) further comprises:

generating a truth table vector for each node of the second list; and

storing the truth table vectors with the second list, wherein each truth table vector identifies the values of the corresponding one of the first plurality of nodes as a function of the values of the second plurality of nodes.

4. A method of tracing any node of a circuit design in an emulator, the method comprising:

(a) generating a first net list identifying a first plurality of nodes of the circuit design;

(b) creating a second net list identifying a second plurality of nodes of the circuit design;

(c) determining a first set of input nodes from the first plurality of nodes; and

(d) using the first set of input nodes to identify a value of a signal at a first one of the second plurality of nodes.

5. The method of claim 4, further comprising generating a first truth table vector which encodes a set of possible values for the first one of the second plurality of nodes, based on different values of the first set of input nodes.

6. The method of claim 5, further comprising using the values of the first set of input nodes as an index into the truth table vector.

7. The method of claim 4, wherein the using operation of (d) comprises:

accessing the set of input nodes to identify a value of a signal at a second one of the second plurality of nodes; and

using the value of the signal at the second one of the second plurality of nodes to determine the value of the signal at the first one of the second plurality of nodes.

8. An emulation system comprising:

(a) means for maintaining relationships between a first plurality of nodes and a second plurality of nodes of a circuit design, including how values of the first plurality of nodes are to be determined based on the second plurality of nodes;

(b) means for accessing values of the second plurality of nodes; and

(c) means for determining the values of the first plurality of nodes based at least in part on both the values of the second plurality of nodes and the relationships between the second plurality of nodes and the first plurality of nodes.

9. The emulation of claim 8, wherein the maintaining means comprises:

means for generating a first list listing the second plurality of nodes; and

means for generating a second list listing the first plurality of nodes, wherein each node of the second list is defined in terms of selected ones of the second plurality of nodes.

10. The emulation system of claim 9, wherein the maintaining means comprises:

means for generating a truth table vector for each node of the second list; and

means for storing the truth table vectors with the second list, wherein each truth table vector identifies the values of the corresponding one of the first plurality of nodes as a function of the values of the second plurality of nodes.