Compiler-oriented apparatus for parallel compilation, simulation and execution of computer programs and hardware models

• US 5,999,734 A
• Filed: 10/21/1997
• Issued: 12/07/1999
• Est. Priority Date: 10/21/1997
• Status: Expired due to Term

• Current Assignee: FTL Systems Incorporated
• Original Assignee: FTL Systems Incorporated
• Inventors: Willis, John Christopher, Newshutz, Robert Neill
• Primary Examiner(s): An, Meng-Ai T.
• Assistant Examiner(s): EL HADY, NABIL M
• Application Number:
  US08/954,843
• Time in Patent Office: 777 Days
• Field of Search: 395/800.01, 395/800.15, 395/800.28, 395/800.09, 395/800.37, 395/200.31, 395/701, 395/705, 395/706, 709/200, 709/201, 712/1, 712/9, 712/15, 712/28, 712/37
• US Class Current: 717/149
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 2117/08 HW-SW co-design, e.g. HW-SW partitioning
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 8/10 Requirements analysis; Specification techniques
• CPC Class Codes: G06F 8/30 Creation or generation of source code
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3897 with adaptable data path

Abstract

A distributed, compiler-oriented database is disclosed with operating modes including parallel compilation, parallel simulation and parallel execution of computer programs and hardware models. The invention utilizes a hardware apparatus consisting of shared memory multiprocessors, optionally augmented by processors with re-configurable logic execution pipelines or independently scheduled re-configurable logic blocks and a software database apparatus, manifest in the hardware apparatus, in order to efficiently support parallel database clients such as a source code analyzer, an elaborator, an optimizer, mapping and scheduling, code generation, linking/loading, execution/simulation, debugging, profiling, user interface and a file interface.

Claims

1. A parallel processor system with at least one node programmed to execute a distributed, compiler-oriented database, the parallel processor system including compilation, simulation and/or software execution operating modes, and comprising:

at least two processors;

memory operationally connected to at least one processor wherein the memory is either local memory or shared memory;

interconnection mechanisms for connecting the at least two processors and the memory; and

re-configurable logic elements, wherein the programmed node is augmented to include a plurality of clients which may perform one or more of the following functions on the distributed, compiler-oriented database selected from a group of;

incremental analysis of source code into the database;

incremental elaboration and/or in-lining of previously analyzed information into the database to yield new or revised database entries;

incremental optimization which transform database contents to yield more efficient simulation, more efficient execution or more observable execution;

incremental code generation, assembly and linking which transform database contents to yield representations directly executable on a combination of programmable processors and reconfigurable logic elements;

runtime, I/O and file systems operations which provide for scheduling, communication and callbacks within and among directly executable simulations/executions;

debugging which provide for interactively starting, stopping and probing the state of simulation/execution;

profiling or event logging of simulation/execution in order to make simulation/execution result accessible to external tools or users; and

graphical interactive user interface transfers wherein the database may coherently cache information having utility on said at least one node.

2. The parallel processor system of claim 1 wherein at least one of the at least two processors is augmented with re-configurable logic execution pipelines dispatched by action of a register to register instruction from an instruction stream of at least one of the at least two processors.

3. The parallel processor system of claim 1 wherein the client operates between at least two communicating operating system processors so as to provide additional addressable memory, software protection and to emulate a target software execution environment.

4. The parallel processor system of claim 2 wherein the client operates between at least two communicating operating system processes so as to provide additional addressable memory, software protection and to emulate a target software execution environment.

5. The parallel processor system of claim 1 wherein the plurality of clients incrementally change source code through incremental and coherent changes in the database to achieve incrementally altered and repartitioned simulation/execution between processors and re-configurable logic devices, the changes in source code preserve simulation/execution state in order to meet evolving requirements for interrupting simulation/execution.

6. The parallel processor system of claim 1 wherein the interrupting of simulation/execution may include actions selected from the group of triggering callbacks, callbacks, substituting event-driven/cycle-driven/continuous-domain algorithms or generate intermediate simulation/execution state require for more detailed debug, display or profiling.

7. The parallel processor system of claim 2 wherein the plurality of clients incrementally change source code through incremental and coherent in the database to achieve incrementally altered and repartitioned simulation/execution between processors and re-configurable logic devices, the changes in source code preserve simulation/execution state in order to meet evolving requirements for interrupting simulation/execution.

8. The parallel processor system of claim 7 wherein the interrupting of simulation/execution may include actions selected from the group of triggering callbacks, callbacks, substituting event-driven/cycle-driven/continuous-domain algorithms or generate intermediate simulation/execution state required for more detailed debug, display or profiling.

9. The parallel processor system of claim 1 wherein relation information contained on the database relating information resident on a node and information only present on a remote node is represented by a remote proxy record, wherein the remote proxy record may provide for coherent caching of the information on the remote node using memory availability and coherence to limit cached copy lifetime.

10. The parallel processor system of claim 2 wherein relation information contained on the database relating information resident on a node and information only present on a remote node is represented by a remote proxy record, wherein the remote proxy record may provide for coherent caching of the information on the remote node using memory availability and coherence to limit cached copy lifetime.

11. A parallel processor system of claim 1 wherein analysis, elaboration and runtime dependency relations between database information may trigger compilation, simulation or execution client activity on the same or other nodes such that the database couples the trigger and the related compilation, simulation or execution, independent of the location of information and clients on various nodes and components of the node.

12. A parallel processor system of claim 2 wherein analysis, elaboration and runtime dependency relations between database information may trigger compilation, simulation or execution client activity on the same or other nodes such that the database couples the trigger and the related compilation, simulation or execution, independent of the location of information and clients on various nodes and components of the node.

13. A parallel processor system of claim 1 wherein the elaborator client operation can produce elaborated database objects prior to code generation and wherein database objects resulting from elaborated re-use database objects resulting from operation of the analyzer client or objects generated by previous operation of the elaborator client.

14. A parallel processor system of claim 2 wherein elaborator client operation can produce elaborated database objects prior to code generation and wherein database objects resulting from elaboration re-use database objects resulting from operation of the analyzer client or objects generated by previous operation of the elaborator client.

36. The processor system of claim 1 wherein at least one of the at least two processors is augmented with re-configurable logic execution pipelines dispatched by action of instructions mapped to a fixed address from the instruction stream of the at least two processors.

37. The parallel processor system of claim 36 wherein the client operates between at least two communicating operating system processors so as to provide additional addressable memory, software protection and to emulate a target software execution environment.

38. The parallel processor system of claim 36 wherein the plurality of clients incrementally change source code through incremental and coherent changes in the database to achieve incrementally altered and repartitioned simulation/execution between processors and re-configurable logic devices, the changes in source code preserve simulation/execution state in order to meet evolving requirements for interrupting simulation/execution.

39. The parallel processor system of claim 38 wherein the interrupting of simulation/execution may include actions selected from the group of triggering callbacks, callbacks, substituting event-driven/cycle-driven/continuous-domain algorithms or generate intermediate simulation/execution state required for more detailed debug, display or profiling.

40. The parallel processor system of claim 36 wherein relation information contained on the database relating information resident on a node and information only present on a remote node is represented by a remote proxy record, wherein the remote proxy record may provide for coherent caching of the information on the remote node using memory availability and coherence to limit cached copy lifetime.

41. A parallel processor system of claim 36 wherein analysis, elaboration and runtime dependency relations between database information may trigger compilation, simulation or execution client activity on the same or other nodes such that the database couples the trigger and the related compilation, simulation or execution, independent of the location of information and clients on various nodes and components of the node.

42. A parallel processor system of claim 36 wherein the elaborator client operation can produce elaborated database objects prior to code generation and wherein database objects resulting from elaboration re-use database resulting from operation of the analyzer client or objects generated by previous operation of the elaborator client.

43. The processor system of claim 1 wherein the at least two processors each support a configurable instruction set architecture and wherein at least one of the at least two processors is augmented with reconfigurable logic execution pipelines.

15. A parallel processor system with at least one node programmed to execute a distributed, complier-oriented database, the parallel processor system including compilation, simulation and/or software execution operating modes, and comprising:

at least two processor;

memory operationally connected to at least one processor wherein the memory is either local memory or shared memory; and

interconnection mechanisms for connecting the at least two processors and the memory;

wherein the programmed node is augmented to include a plurality of clients which may perform one or more of the following functions on the distributed, compiler-oriented database selected from a group of;

incremental analysis of source code into the database;

incremental elaboration and/or in-lining of previously analyzed information into the data base to yield new or revised database entries;

incremental optimization which transform database contents to yield more efficient simulation, more efficient execution or more observable execution;

incremental code generation, assembly and linking which transform database contents to yield representations directly executable on a combination of programmable processors and reconfigurable logic elements;

runtime I/O and file systems operations which provide for scheduling communication and callbacks within and among directly executable simulations/executions;

debugging which provide for interactively starting, stopping and probing the state of simulation/execution;

profiling or event logging of simulation/execution in order to make simulation/execution results accessible to external tools or users; and

graphical interactive user interface transfers wherein the database may coherently cache information having utility on said at least one node.

16. The parallel processor system of claim 15 wherein the client operates between at least two communicating operating system processes so as to provide additional addressable memory, software protection and to emulate a target software execution environment.

17. The parallel processor system claim 15 wherein the plurality of clients incrementally change source code through incremental and coherent changes in the database to achieve incrementally altered and repartitioned simulation/execution between processors and re-configurable logic devices, the changes in source code preserve simulation/execution state in order to meet evolving requirements for interrupting simulation/execution.

18. The parallel processor system of claim 17 wherein the interrupting of simulation/execution may include actions selected from the group of triggering callbacks, callbacks, substituting event-driven/cycle-driven/continuous-domain algorithms or generate intermediate simulation/execution state required for more detailed debug, display or profiling.

19. The parallel processor system of claim 15 wherein relation information contained on the database relating information resident on a node and information only present on a remote node is represented by a remote proxy record, wherein the remote proxy record may provide for coherent caching of the information on the remote node using memory availability and coherence to limit cached copy lifetime.

20. A parallel processor system of claim 15 wherein analysis, elaboration and runtime dependency relations between database information may trigger compilation, simulation or execution client activity on the same or other nodes such that the database couples the trigger and the related compilation, simulation or execution, independent of the location of information and clients on various nodes and components of the node.

21. A parallel processor system of claim 15 wherein the elaborator client operation can produce elaborated database objects prior to code generation and wherein database objects resulting from elaboration re-use database objects resulting from operation of the analyzer client or objects generated by previous operation of the elaborator client.

22. The processor system of claim 15 wherein at least one of the at least two processors is augmented with re-configurable logic execution pipelines dispatched by action of register to register instruction from an instruction stream of at least one of the at least two processors.

23. The parallel processor system of claim 22 wherein the client operates between at least two communicating operating system processors so as to provide additional addressable memory, software protection and to emulated a target software execution environment.

24. The parallel processor system of claim 22 wherein the plurality of clients incrementally change source code through incremental and coherent changes in the database to achieve incrementally altered and repartitioned simulation/execution between processors and re-configurable logic devices, the changes in source code preserve simulation/execution state in order to meet evolving requirements for interrupting simulation/execution.

25. The parallel processor system of claim 24 wherein the interrupting of simulation/execution may include actions selected from the group of triggering callbacks, callbacks, substituting event-driven/cycle-driven/continuous-domain algorithms or generate intermediate simulation/execution state required for more detailed debug, display or profiling.

26. The parallel processor system of claim 22 wherein relation information contained on the database relating information resident on a node and information only present on a remote node is represented by a remote proxy record, wherein the remote proxy record may provide for coherent caching of the information on the remote node using memory availability and coherence to limit cached copy lifetime.

27. A parallel processor system of claim 22 wherein analysis, elaboration and runtime dependency relations between database information may trigger compilation, simulation or execution client activity on the same or other nodes such that the database couples the trigger and the related compilation, simulation or execution, independent of the location of information and clients on various nodes and components of the node.

28. A parallel processor system of claim 22 wherein the elaborator client operation can produce elaborated database objects prior to code generation and wherein database objects resulting from elaboration re-use database objects resulting from operation of the analyzer client or objects generated by previous operation of the elaborator client.

29. The processor system of claim 15 wherein at least one of the at least two processors is augmented with re-configurable logic execution pipelines dispatched by action of instruction mapped to a fixed address from the instruction stream of the at least two processors.

30. The parallel processor system of claim 29 wherein the client operates between at least two communicating operating system processes so as to provide additional addressable memory, software protection and to emulated a target software execution environment.

31. The parallel processor system of claim 29 wherein the plurality of clients incrementally change source code through incremental and coherent changes in the database to achieve incrementally altered and repartitioned simulation/execution between processors and re-configurable logic devices, the changes in source code preserve simulation/execution state in order to meet evolving requirements for interrupting simulation/execution.

32. The parallel processor system of claim 31 wherein the interrupting of simulation/execution may include actions selected from the group of triggering callbacks, callbacks, substituting event-driven/cycle-driven/continuous-domain algorithms or generate intermediate simulation/execution state required for more detailed debug, display or profiling.

33. The parallel processor system of claim 29 wherein relation information contained on the database relating information resident on a node and information only present on a remote node is represented by a remote proxy record, wherein the remote proxy record may provide for coherent caching of the information on the remote node using memory availability and coherence to limit cached copy lifetime.

34. A parallel processor system of claim 29 wherein analysis, elaboration and runtime dependency relations between database information may trigger compilation, simulation or execution client activity on the same or other nodes such that the database couples the trigger and the related compilation, simulation or execution, independent of the location of information and clients on various nodes and components of the node.

35. A parallel processor system of claim 29 wherein the elaborator client operation can produce elaborated database objects prior to code generation and wherein database objects resulting from elaboration re-use database objects resulting from operation of the analyzer client or objects generated by previous operation of the elaborator client.

44. The processor system of claim 15 wherein the at least two processors each support a reconfigurable instruction set architecture and wherein at least one of the at least two processors is augmented with reconfigurable logic execution pipelines.