System and method for dynamically allocating accelerated graphics port memory space
First Claim
1. A computer system having a core logic chipset which connects a computer processor and memory to an accelerated graphics port (AGP) bus and a peripheral component interconnect (PCI) bus, said system comprising:
- a system processor executing software instructions and generating graphics data;
a system memory having an addressable memory space comprising a plurality of bytes of storage, wherein each of the plurality of bytes of storage has a unique address;
the software instructions and the graphics data being stored in some of the plurality of bytes of storage of said system memory, wherein the graphics data is stored in a plurality of pages of graphics data, each of the plurality of pages of graphics data comprising a number of the plurality of bytes of storage;
an accelerated graphics port (AGP) processor connected to an AGP bus and generating video display data from the graphics data and adapted for a video display to display the video display data;
a core logic chipset having a first interface logic for connecting said system processor to said system memory;
said core logic chipset having a second interface logic for connecting said system processor and said system memory to input-output devices on a peripheral component interconnect (PCI) bus;
said core logic chipset having a third interface logic for connecting said system processor and said system memory to said AGP bus;
said core logic chipset having a fourth interface logic for connecting said AGP bus to said PCI bus;
said second interface logic having a base address register;
said fourth interface logic having an AGP device address space size register;
said AGP device address space size register having a value which indicates the size of an AGP device address space required by said AGP processor; and
said fourth interface logic communicating the value in said AGP device address space size register to said second interface logic so that a corresponding value is stored in said base address register, wherein the corresponding value stored in said base address register is used by computer system memory mapping software to configure the size of the AGP device address space, the AGP device address space being within the addressable memory space, and said base address register storing a base address value of the AGP device address space after the size of the AGP device address space is configured.
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Accused Products
Abstract
A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. Contiguous virtual memory address space must be allocated for the AGP device within the addressable memory space of the computer system, typically 4 gigabytes using 32 bit addressing. The required amount of virtual memory address space for AGP is determined from the AGP device and the information is put into a register of the core logic so that the computer system software may allocate the required amount of memory and assign a base address thereto during computer system startup or POST.
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Citations
26 Claims
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1. A computer system having a core logic chipset which connects a computer processor and memory to an accelerated graphics port (AGP) bus and a peripheral component interconnect (PCI) bus, said system comprising:
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a system processor executing software instructions and generating graphics data; a system memory having an addressable memory space comprising a plurality of bytes of storage, wherein each of the plurality of bytes of storage has a unique address; the software instructions and the graphics data being stored in some of the plurality of bytes of storage of said system memory, wherein the graphics data is stored in a plurality of pages of graphics data, each of the plurality of pages of graphics data comprising a number of the plurality of bytes of storage; an accelerated graphics port (AGP) processor connected to an AGP bus and generating video display data from the graphics data and adapted for a video display to display the video display data; a core logic chipset having a first interface logic for connecting said system processor to said system memory; said core logic chipset having a second interface logic for connecting said system processor and said system memory to input-output devices on a peripheral component interconnect (PCI) bus; said core logic chipset having a third interface logic for connecting said system processor and said system memory to said AGP bus; said core logic chipset having a fourth interface logic for connecting said AGP bus to said PCI bus; said second interface logic having a base address register; said fourth interface logic having an AGP device address space size register; said AGP device address space size register having a value which indicates the size of an AGP device address space required by said AGP processor; and said fourth interface logic communicating the value in said AGP device address space size register to said second interface logic so that a corresponding value is stored in said base address register, wherein the corresponding value stored in said base address register is used by computer system memory mapping software to configure the size of the AGP device address space, the AGP device address space being within the addressable memory space, and said base address register storing a base address value of the AGP device address space after the size of the AGP device address space is configured. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A method, in a computer system having a core logic chipset which connects a computer processor and memory to an accelerated graphics port (AGP) bus and a peripheral component interconnect (PCI) bus, of determining and setting the size of AGP device address space required by an AGP graphics processor connected to the AGP bus, said method comprising the steps of:
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reading configuration registers of an accelerated graphics port (AGP) processor; determining the size of an AGP device address space required by the AGP processor based on information from the configuration registers of the AGP processor; writing a first binary value to a first register to represent the determined size of the AGP device address space; configuring a second binary value in a second register, wherein the second binary value is derived from the first binary value and indicates the determined size of the AGP device address space; reading the second register to obtain the determined size of the AGP device address space; allocating the determined size of the AGP device address space based on the second binary value; and writing a base address of the allocated AGP device address space in the second register. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26)
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Specification