Low power rectifier circuit for implantable medical device

• US 5,999,849 A
• Filed: 09/12/1997
• Issued: 12/07/1999
• Est. Priority Date: 09/12/1997
• Status: Expired due to Term

• Current Assignee: Alfred E. Mann Foundation For Scientific Research
• Original Assignee: Alfred E. Mann Foundation For Scientific Research
• Inventors: Gord, John C., Canfield, Lyle Dean
• Primary Examiner(s): Kamm, William E.
• Assistant Examiner(s): LAYNO, CARL HERNANDZ
• Application Number:
  US08/928,871
• Time in Patent Office: 816 Days
• Field of Search: 327/104, 327/124, 607/2, 607/36, 607/122, 607/116, 607/5, 607/35, 600/373, 600/377, 363/127
• US Class Current: 607/2
• CPC Class Codes: A61N 1/378 Electrical supply
• CPC Class Codes: H02M 7/219 in a bridge configuration

Abstract

A low power switched rectifier circuit is realized using P-MOS and N-MOS FET switches that are turned ON/OFF at just the right time by a detector and inverter circuit (which form an integral part of the rectifier circuit) to rectify an incoming ac signal in a highly efficient manner. Parasitic diodes and transistors that form an integral part of the FET circuitry respond to and rectify the incoming signal during start up, i.e., when no supply voltage is yet present, thereby providing sufficient operating voltage for the FET switches to begin to perform their intended rectifying function. In the absence of an incoming ac signal, i.e., during the time between biphasic pulses, the rectifier circuit is biased with an extremely small static bias current; but in the presence of an incoming ac signal, at a time when the positive and negative phases of the incoming signal are to be connected to positive and negative supply lines, a much larger dynamic bias current is automatically triggered.

Claims

1. A low power switched rectifier circuit comprising:

first and second voltage rails (120,

     122);

a storage capacitor (C1) connected between the first and second voltage rails;

first and second input lines (LINE 1, LINE

     2);

a first switch (M1) connecting the first input line to the first voltage rail;

a second switch (M2) connecting the second input line to the first voltage rail;

a third switch (M3) connecting the first input line to the second voltage rail;

a fourth switch (M4) connecting the second input line to the second voltage rail;

a detector circuit for each of said first, second, third, and fourth switches, respectively, powered by voltage on the storage capacitor, that automatically controls its respective switch to close and open as a function of the voltage signal appearing on the first input line relative to the second input line such that, in concert, the first and fourth switches close and the second and third switches open in response to a positive signal on the first input line relative to the second input line, and such that second and third switches close and the first and fourth switches open in response to a negative signal on the first input line relative to the second input line, whereby the first input line is automatically connected to the first voltage rail and the second input line is automatically connected to the second voltage rail whenever a positive signal appears on the first input line relative to the second input line, and whereby the first input line is automatically connected to the second voltage rail and the second input line is automatically connected to the first voltage rail whenever a negative signal appears on the first input line relative to the second input line; and

startup means for supplying the storage capacitor with an initial voltage sufficient to power each of the detector circuits;

said low power switched rectifier circuit wherein all of said first, second, third, and fourth switches and respective detector circuits are all part of a single integrated circuit.

2. The low power switched rectifier circuit of claim 1 wherein the first, second, third and fourth switches and respective detector circuits comprise N-MOS and P-MOS complimentary field-effect transistors.

3. The low power switched rectifier circuit of claim 2 wherein the startup means comprises parasitic P-N junctions present in the N-MOS and P-MOS complimentary field-effect transistors.

4. The low power switched rectifier circuit of claim 2 wherein said single integrated circuit further includes a bias generator circuit that generates a plurality of bias signals used by the respective detector circuits to detect the presence of an incoming voltage signal on the first and second input signal lines.

5. The low power switched rectifier circuit of claim 4 wherein the bias generator circuit generates a first bias signal that is a fixed amount less than the voltage present on the storage capacitor as sensed on the first voltage rail, and wherein the first detector circuit closes the first switch to connect the first input line to the first voltage rail only when the incoming voltage signal on the first input line exceeds the first bias signal.

6. The low power switched rectifier circuit of claim 4 wherein the bias generator circuit generates a first bias signal that is a fixed amount less than the voltage present on the storage capacitor as sensed on the first voltage rail, and wherein the first detector circuit closes the first switch to connect the second input line to the first voltage rail only when the incoming voltage signal on the second input line exceeds the first bias signal.

7. The low power switched rectifier circuit of claim 6 wherein the bias generator circuit includes means for dynamically changing the first bias signal from a first value to a second value whenever an incoming voltage signal is present on the first input line relative to the second input line.

8. The low power switched rectifier circuit of claim 4 wherein the bias generator circuit generates a second bias signal that is a fixed amount smaller than a negative voltage present on the storage capacitor as sensed at the second voltage rail relative to the first voltage rail, and wherein the third detector circuit closes the third switch to connect the first input line to the second voltage rail only when the incoming voltage signal on the first input line relative to the second voltage line is a negative voltage greater than the second bias signal.

9. The low power switched rectifier circuit of claim 4 wherein the bias generator circuit generates a second bias signal that is a fixed amount smaller than a negative voltage present on the storage capacitor as sensed at the second voltage rail relative to the first voltage rail, and wherein the third detector circuit closes the third switch to connect the second input line to the second voltage rail only when the incoming voltage signal on the second input line relative to the second voltage line is a negative voltage greater than the second bias signal.

10. The low power switched rectifier circuit of claim 9 wherein the bias generator circuit includes means for dynamically changing the second bias signal from a first value to a second value whenever an incoming voltage signal is present on the second input line relative to the first input line.

11. An implantable device comprising;

an hermetically sealed case;

means for coupling power signals into said hermetically sealed case;

a rectifier circuit for rectifying the incoming power signals and generating an operating voltage therefrom; and

electronic circuits within said hermetically sealed case and powered by said operating voltage for performing specified functions;

said rectifier circuit including a pair of input lines on which the power signal is received,

a pair of output lines on which the operating voltage is made available,

N-MOS and P-MOS field effect transistors (FET'"'"'S) for automatically connecting an appropriate one of the pair of input lines to an appropriate one of the pair of output lines in synchrony with positive and negative amplitude variations of the power signals, and

a filter capacitor connected between the pair of output lines;

wherein N-MOS and P-MOS switches further comprise;

a first P-MOS FET (M1) that, when turned on, connects a first one of the input lines (LINE

     1) to a first one of the output lines (V+);

a second P-MOS FET (M2) that, when turned on, connects a second one of the input lines (LINE

     2) to the first one of the output lines (V+);

a first N-MOS FET (M3) that, when turned on, connects the first one of the input lines (LINE

     1) to a second one of the output lines (V-);

a second N-MOS FET (M4) that, when turned on, connects the second one of the input lines (LINE

     2) to the second one of the output lines (V-);

a first detector circuit that turns the first P-MOS FET switch (M1) on only when the power signal on LINE 1 relative to LINE 2 has a positive amplitude exceeding a first threshold value;

a second detector circuit that turns the second P-MOS FET switch (M2) on only when the power signal on LINE 2 relative to LINE 1 has a positive amplitude exceeding the first threshold value;

a third detector circuit that turns the first N-MOS FET switch (M3) on only when the power signal on LINE 1 relative to LINE 2 has a negative amplitude exceeding a second threshold value; and

a fourth detector circuit that turns the second N-MOS FET switch (M4) on only when the power signal on LINE 2 relative to LINE 1 has a negative amplitude exceeding the second threshold value;

said implantable device wherein each of the first, second, third, and fourth detector circuits further comprise a complementary N-MOS and P-MOS transistor pair connected as a detector circuit to be biased ON only when a power signal greater than a bias reference voltage is present on the pair of input lines.

12. The implantable device of claim 11 wherein the complementary N-MOS and P-MOS transistor pair of each detector circuit has a first bias reference voltage connected to a gate terminal of its P-MOS transistor, and a second bias reference voltage connected to a gate terminal of its N-MOS transistor.

13. The implantable device of claim 12 further including a bias generator circuit that generates the first and second reference voltages, and wherein the bias generator circuit includes means for dynamically setting the first and second reference voltages to an operational level when a power signal is present on the pair of input lines, and to a low power stand-by level when a power signal is not present on the pair of input lines.

14. The implantable device of claim 11 further including a complementary N-MOS and P-MOS inverter circuit interposed between each detector circuit and the respective first/second P-MOS/N-MOS FET switch controlled by the detector circuit.

15. An implantable medical device comprising:

an hermetically sealed case;

means for coupling power signals into said hermetically sealed case;

a rectifier circuit for rectifying the incoming power signals and generating an operating voltage therefrom; and

electronic circuits within said hermetically sealed case and powered by said operating voltage for performing specified functions;

said rectifier circuit including a pair of input lines on which the power signal is received,

a pair of output lines on which the operating voltage is made available,

N-MOS and P-MOS field effect transistors (FET'"'"'S) for automatically connecting an appropriate one of the pair of input lines to an appropriate one of the pair of output lines in synchrony with positive and negative amplitude variations of the power signals, and

a filter capacitor connected between the pair of output lines;

said implantable device further including startup means for providing a voltage to the filter capacitor connected between the pair of output lines at a time when no operating voltage is present on said filter capacitor.

16. The implantable device of claim 15 wherein the startup means comprises parasitic diodes within the N-MOS FET switches, and parasitic PNP bipolar transistors within the P-MOS FET switches, which parasitic diodes and transistors are sufficiently forward biased by an initial power signal on the pair of input lines to cause an initial operating voltage derived from the initial power signal to be stored on said filter capacitor.

17. A low power rectifier circuit comprising:

means for receiving a pulsed power signal;

a pair of input lines on which the pulsed power signal is received;

a pair of output lines on which the operating voltage is made available;

N-MOS and P-MOS field effect transistor (FET) switches that automatically connect an appropriate one of the pair of input lines to an appropriate one of the pair of output lines is synchrony with positive and negative pulses of the pulsed power signal;

a filter capacitor connected between the pair of output lines;

wherein said switches further comprise;

a first P-MOS FET (M1) that, when turned on, connects a first one of the input lines (LINE

     1) to a first one of the output lines (V+);

a second P-MOS FET (M2) that, when turned on, connects a second one of the input lines (LINE

     2) to the first one of the output lines (V+);

a first N-MOS FET (M3) that, when turned on, connects the first one of the input lines (LINE

     1) to a second one of the output lines (V-);

a second N-MOS FET (M4) that, when turned on, connects the second one of the input lines (LINE

     2) to the second one of the output lines (V-); and

a detector circuit that when there is a positive pulse within the pulsed power signal on LINE 1 relative to LINE 2 turns the first P-MOS FET (M1) on, the second N-MOS FET (M4) on, and maintains the second P-MOS FET (M2) off, and the first N-MOS FET (M3) off, and when there is a negative pulse within the pulsed power signal on LINE 1 relative to LINE 2, turns the second P-MOS FET (M2) on, the first N-MOS FET (M3) on and maintains the first P-MOS FET (M1) off, and the second N-MOS FET (M4) off;

wherein said detector circuit further comprises;

a first detector circuit that turns the first P-MOS FET (MI) on only when there is a positive pulse within the pulsed power signal on LINE 1 relative to LINE 2 that has an amplitude exceeding a first threshold value;

a second detector circuit that turns the second P-MOS FET (M2) on only when there is a positive pulse within the pulse power signal on LINE 2 relative to LINE 1 that has an amplitude exceeding a first threshold value;

a third detector circuit that turns the first N-MOS FET (M3) on only when there is a negative pulse within the pulse power signal on LINE 1 relative to LINE 2 that has a negative amplitude exceeding a second threshold value;

a fourth detector circuit that turns the second N-MOS FET (M4) on only when there is a negative pulse within the pulse power signal on LINE 2 relative to LINE 1 that has a negative amplitude exceeding a second threshold value;

said low power rectifier circuit wherein each of the first, second, third, and fourth detector circuits include a complementary N-MOS and P-MOS transistor pair connected as a detector circuit to be biased ON only when a pulse of the pulsed power signal present on the pair of the input lines has an amplitude greater than a bias reference voltage.

18. The implantable device of claim 17 wherein the complementary N-MOS and P-MOS transistor pair of each detector circuit has a first bias reference voltage connected to a gate terminal of its P-MOS transistor, and a second bias reference voltage connected to a gate terminal of its N-MOS transistor.

19. The implantable device of claim 18 further including a bias generator circuit that generates the first and second reference voltages, and wherein the bias generator circuit includes means for dynamically setting the first and second reference voltages to an operational level when a power signal is present on the pair of input lines, and to a low power stand-by level when a power signal is not present on the pair of input lines.

20. The implantable device of claim 18 further including a complementary N-MOS and P-MOS inverter circuit interposed between each detector circuit and the respective first/second P-MOS/N-MOS FET switch controlled by the detector circuit.

21. A low power rectifier circuit implantable device comprising:

means for receiving a pulsed power signal;

a pair of input lines on which the pulsed sower signal is received;

a pair of output lines on which the operating voltage is made available;

a filter capacitor connected between the pair of output lines;

N-MOS and P-MOS field effect transistor (FET) switches that automatically connect an appropriate one of the pair of input lines to an appropriate one of the pair of output lines in synchrony with positive and negative pulses of the pulsed power signal;

further comprising startup means for providing a voltage to the filter capacitor connected between the pair of output lines at a time when no operating voltage is present on said filter capacitor.

22. The implantable device of claim 21 wherein the startup means comprises parasitic diodes within the N-MOS FET switches, and parasitic PNP bipolar transistors within the P-MOS FET switches, which parasitic diodes and transistors are sufficiently forward biased by an initial power signal on the pair of input lines to cause an initial operating voltage derived from the initial power signal to be stored on said filter capacitor.

23. A low power rectifier circuit comprising:

means for receiving a pulsed power signal;

a pair of input lines on which the pulsed power signal is received;

a pair of output lines on which the operating voltage is made available;

N-MOS and P-MOS field effect transistor (FET) switches that automatically connect an appropriate one of the pair of input lines to an appropriate one of the pair of output lines in synchrony with positive and negative pulses of the pulsed power signal; and

a filter capacitor connected between the pair of output lines;

wherein the pulsed power signal comprises a pulse train of biphasic pulses, each biphasic pulse of the pulse train having a negative pulse and a positive pulse;

wherein the frequency of the biphasic pulses in the pulse train ranges from 10 to 500,000 biphasic pulses per second, and wherein each positive and negative pulse within each biphasic pulse has a pulse width of between about 1 to 3 microseconds.