Method and apparatus for coupling signals between two circuits operating in different clock domains

• US 6,000,022 A
• Filed: 10/10/1997
• Issued: 12/07/1999
• Est. Priority Date: 10/10/1997
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Manning, Troy A.
• Primary Examiner(s): Chan, Eddie P.
• Assistant Examiner(s): Ellis, Kevin L.
• Application Number:
  US08/948,712
• Time in Patent Office: 788 Days
• Field of Search: 711/104, 711/105, 711/167, 710/52, 713/400, 713/401
• US Class Current: 711/167
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: H04L 7/0012 by comparing receiver clock with transmitter clock

Abstract

A coupling circuit for coupling a first signal generated in a first circuit operating in a first clock domain to a second circuit operating in a second clock domain. The coupling circuit includes a first gate for coupling the first signal to a first logic circuit unless the coupling circuit has already applied a signal to the second circuit. The first logic circuit includes a pair of second gates that are enabled by respective rising and falling edges of the first clock signal. Thus, each of the second gates generates an output signal on respective transitions of the first clock signal as long as the first gate is coupling the first signal to the first logic circuit. The first logic circuit also includes a pair of latches coupled to respective outputs of the second gates. Each of the latches is set by its respective second gate generating the output signal. The second logic gates are coupled to a second logic circuit having a pair of third gates that are enabled by respective rising and falling edges of the second clock signal. Thus, each of the second gates generates an output signal on respective transitions of the second clock signal if the latch to which it is connected is generating an output signal. The output signal is also used as the reset signal to disable the first gate and reset the latches. Since the output signal is generated on the first transition of the first clock signal after the first signal is applied to the coupling circuit, the coupling circuit generates a single output signal that is synchronized to the second clock signal.

Claims

1. An apparatus for applying a second signal to a second device operating in a second clock domain defined by a second clock signal responsive to a first signal received from a first device operating in a first clock domain defined by a first clock signal, the apparatus comprising:

a first logic circuit coupled to receive the first signal and the first clock signal, the first logic circuit generating an intermediate signal responsive to each transition of the first clock signal subsequent to the first signal being received unless a reset signal is being applied to the first logic circuit, the first logic circuit comprising;

a third logic circuit to receive the first signal and the reset signal, the third logic circuit generating an output signal responsive to the first signal unless the reset signal is being applied to the third logic circuit;

a clocking circuit generating enable pulses responsive to respective transitions of the first clock signal, the clocking circuit generating enable pulses responsive to both positive and negative transitions of the first clock signal; and

a fourth logic circuit coupled to receive the output signal of the third logic circuit and the enable pulses from the first clocking circuit, the fourth logic circuit generating the intermediate signal responsive to receiving the output signal from the third logic circuit and one of the enable pulses, the fourth logic circuit comprising first and second gating circuit receiving the output signal of the third logic circuit, the first gating circuit generating the intermediate signal responsive to receiving the output signal from the third logic circuit and an enable pulse generated responsive to a positive transition of the first clock signal, the second logic gate generating the intermediate signal responsive to receiving the output signal from the third logic circuit and an enable pulse generated responsive to a negative transition of the first clock signal; and

a second logic circuit coupled to the first logic circuit to receive the intermediate signal and the second clock signal, the second logic circuit generating the second signal responsive to a transition of the second clock signal subsequent to the intermediate signal being generated, the second logic circuit generating the reset signal responsive to the second signal.

2. The coupling circuit of claim 1 wherein the fourth logic circuit further comprises a latch circuit continuously generating the intermediate signal responsive to receiving the output signal from the third logic circuit and one of the enable pulses until the second logic circuit generates the reset signal.

3. An apparatus for applying a second signal to a second device operating in a second clock domain defined by a second clock signal responsive to a first signal received from a first device operating in a first clock domain defined by a first clock signal, the apparatus comprising:

a first logic circuit coupled to receive the first signal and the first clock signal, the first logic circuit generating an intermediate signal responsive to each transition of the first clock signal subsequent to the first signal being received unless a reset signal is being applied to the first logic circuit; and

a second logic circuit coupled to the first logic circuit to receive the intermediate signal and the second clock signal, the second logic circuit generating the second signal responsive to a transition of the second clock signal subsequent to the intermediate signal being generated, the second logic circuit generating the reset signal responsive to the second signal, the second logic circuit comprising;

a clocking circuit generating enable pulses responsive to respective transitions of the second clock signal, the clocking circuit generating enable pulses responsive to both positive and negative transitions of the first clock signal, and

a third logic circuit coupled to receive the intermediate signal from the first logic circuit and the enable pulses from the clocking circuit, the third logic circuit generating the second signal responsive to receiving the intermediate signal from the first logic circuit and one of the enable pulses, the third logic circuit comprising first and second gating circuit receiving the intermediate signal from the first logic circuit, the first gating circuit generating the second signal responsive to receiving the intermediate signal from the first logic circuit and an enable pulse generated responsive to a positive transition of the second clock signal, the second logic gate generating the second signal responsive to receiving the intermediate signal from the first logic circuit and an enable pulse generated responsive to a negative transition of the second clock signal.

4. A coupling circuit for coupling a first signal from a first device operating in one clock domain defined by a first clock signal to a second device operating in a second clock domain defined by a second clock signal, the coupling circuit comprising:

a first clocking circuit generating first enable pulses responsive to respective transitions of the first clock signal, the first clocking circuit generating first enable pulses responsive to both positive and negative transitions of the first clock signal;

a second clocking circuit generating second enable pulses responsive to respective transitions of the second clock signal;

a first gating circuit including a latch circuit generating an intermediate signal until the latch circuit is reset, the latch circuit being reset responsive to an output signal, the first gating circuit generating the intermediate signal responsive to receiving the first signal from the first device and a first enable pulse from the first clocking circuit, the first gating circuit comprising first and second logic gates receiving the first signal, the first logic gate generating the intermediate signal responsive to receiving the first signal and a first enable pulse generated responsive to a positive transition of the first clock signal, the second logic gate generating the intermediate signal responsive to receiving the first signal and a first enable pulse generated responsive to a negative transition of the first clock signal; and

a second gating circuit applying the output signal to the second device responsive to receiving the intermediate signal from the first gating circuit and a second enable pulse from the second clocking circuit.

5. A coupling circuit for coupling a first signal from a first device operating in one clock domain defined by a first clock signal to a second device operating in a second clock domain defined by a second clock signal, the coupling circuit comprising:

a first clocking circuit generating first enable pulses responsive to respective transitions of the first clock signal;

a second clocking circuit generating second enable pulses responsive to respective transitions of the second clock signal, the second clocking circuit generating second enable pulses responsive to both positive and negative transitions of the second clock signal;

a first gating circuit generating an intermediate signal responsive to receiving the first signal from the first device and a first enable pulse from the first clocking circuit; and

a second gating circuit applying the output signal to the second device responsive to receiving the intermediate signal from the first gating circuit and a second enable pulse from the second clocking circuit, the second gating circuit comprising third and fourth logic gates receiving the intermediate signal from the first and second logic gates, respectively, the third logic gate generating the output signal responsive to receiving the intermediate signal from the first logic gate and a second enable pulse generated responsive to a positive transition of the second clock signal, the second logic gate generating the output signal responsive to receiving the intermediate signal from the second logic circuit and a second enable pulse generated responsive to a negative transition of the second clock signal.

6. A coupling circuit for coupling a first signal from a first device operating in one clock domain defined by a first clock signal to a second device operating in a second clock domain defined by a second clock signal, the coupling circuit comprising:

a first clocking circuit generating first enable pulses responsive to respective transitions of the first clock signal;

a second clocking circuit generating second enable pulses responsive to respective transitions of the second clock signal, the second clocking circuit generating second enable pulses responsive to both positive and negative transitions of the second clock signal;

a first gating circuit generating an intermediate signal responsive to receiving the first signal from the first device and a first enable pulse from the first clocking circuit; and

a second gating circuit applying the output signal to the second device responsive to receiving the intermediate signal from the first gating circuit and a second enable pulse from the second clocking circuit, the second gating circuit comprising first and second logic gates receiving the intermediate signal, the first logic gate generating the output signal responsive to receiving the intermediate signal and a second enable pulse generated responsive to a positive transition of the second clock signal, the second logic gate generating the output signal responsive to receiving the intermediate signal and a second enable pulse generated responsive to a negative transition of the second clock signal.

7. A coupling circuit for coupling a first signal from a first device operating in one clock domain defined by a first clock signal to a second device operating in a second clock domain defined by a second clock signal, the coupling circuit comprising:

a logic gate having a signal input terminal, an output terminal, and a control terminal, the signal input terminal being coupled to the first device to receive the first signal, the logic gate coupling the input terminal to the output terminal until a disable input is applied to the control terminal;

a first clocking circuit having a clock input terminal, and an input terminal coupled to the output terminal of the logic gate, the first clocking circuit coupling the input terminal to an output terminal responsive to one transition of the first clock signal;

a first latch circuit having a trigger input coupled to the output terminal of the first clocking circuit, the first latch circuit generating a latched signal at an output terminal responsive to the trigger signal until the latch circuit is reset by a reset signal;

a second clocking circuit having a clock input terminal, and an input terminal coupled to the output terminal of the logic gate, the second clocking circuit coupling the input terminal to an output terminal responsive to another transition of the first clock signal;

a second latch circuit having a trigger input coupled to the output terminal of the second clocking circuit, the second latch circuit generating a latched signal at an output terminal responsive to the trigger signal until the latch circuit is reset by the reset signal;

a third clocking circuit having a clock input terminal, and an input terminal coupled to the output terminal of the first latch circuit, the third clocking circuit coupling the input terminal to an output terminal responsive to one transition of the second clock signal;

a fourth clocking circuit having a clock input terminal, and an input terminal coupled to the output terminal of the second latch circuit, the fourth clocking circuit coupling the input terminal to an output terminal responsive to another transition of the second clock signal;

a combining circuit having first and second input terminals coupled to the output terminals of the third and fourth clocking circuits, respectively, the combining circuit generating an output signal at an output terminal responsive to receiving a latched signal clocked from a respective latch by either said third or said fourth clock circuit, the output signal being coupled to the second device, the output terminal of the combining circuit being coupled to the disable terminal of the logic gate and to the reset terminals of the latch circuits to disable the logic gate and reset the latch circuits responsive to the output signal from the combining circuit.

8. The coupling circuit of claim 7 further comprising:

a signal routing circuit altering the coupling between the respective output terminals of the first and second latch circuits to the input terminals of the third and fourth clocking circuits, the signal routing circuit coupling the output terminal of the first latch circuit to the input terminal of the fourth clock circuit and the output terminal of the second latch circuit to the input terminal of the third clock circuit responsive to a signal routing control signal applied to a control terminal of the signal routing circuit; and

a control circuit coupled to the signal routing circuit, the control circuit applying the signal routing control signal to the control input terminal of the signal routing circuit.

9. The coupling circuit of claim 8 wherein the control circuit comprises a phase comparison circuit receiving the first and second clock signals at first and second input terminals, the control circuit generating the signal routing control circuit as a function of the phase relationship between the first and second clock signals.

10. The coupling circuit of claim 7 wherein the signal routing circuit comprises:

a first pair of inverters having respective inputs coupled to the output terminals of the first and second latch circuits and respective output terminals coupled to respective input terminals of the third and fourth clocking circuits, the first pair of inverters being enable responsive to a first logic level of the signal routing control signal; and

a second pair of inverters having respective inputs coupled to the output terminals of the first and second latch circuits and respective output terminals coupled to respective input terminals of the fourth and third clocking circuits, the second pair of inverters being enable responsive to a second logic level of the signal routing control signal.

11. The coupling circuit of claim 10 wherein the control circuit comprises a phase comparison circuit receiving the first and second clock signals at first and second input terminals, the control circuit generating a signal routing control signal having the first logic level responsive to one timing relationship between the first and second clock circuits and a signal routing control signal having the second logic level responsive to another timing relationship between the first and second clock circuits.

12. A memory device, comprising:

a control circuit adapted to receive a command from an external source and generate control signals responsive thereto, the control circuit including a clock generator circuit adapted to receive an external clock signal and to generate an internal clock signal, a read transfer initiate signal, a write transfer initiate signal, a read data initiate signal, and a write data initiate signal, the timing of the read clock signal and the write clock signal being controlled by an external device;

a memory array coupled to the control circuit, the memory array having a plurality of memory cells adapted to store write data and output read data;

an addressing circuit coupled to the memory array and the control circuit, the addressing circuit adapted to receive addresses from an external source and select a memory cell in the memory array corresponding thereto;

a read data path having a read register coupled to the control circuit, the read register being adapted to couple read data from the memory array to an externally accessible terminal responsive to the read clock signal subsequent to the read data start signal being applied to a control input terminal;

a write data path having a write register coupled to the control circuit, the write register being adapted to couple write data from the externally accessible terminal to the memory array responsive to a write register clock signal subsequent to a write data start signal being applied to a control input terminal;

respective first and second coupling circuits having an input terminal connected to the control circuit to receive a respective transfer initiate signal and an output terminal connected to the control input terminal of a respective register, each of the coupling circuits comprising;

a first clocking circuit generating first enable pulses responsive to respective transitions of a first clock signal synchronized to the internal clock signal;

a second clocking circuit generating second enable pulses responsive to respective transitions of a second clock signal, the timing of the second clocking being controlled by the external device;

a first gating circuit generating an intermediate signal responsive to receiving the respective transfer initiate signal from the control circuit and a first enable pulse from the first clocking circuit; and

a second gating circuit applying the respective data start signal to the respective register responsive to receiving the intermediate signal from the first gating circuit and a second enable pulse from the second clocking circuit.

13. The memory device of claim 12 wherein the second clocking circuit generates second enable pulses responsive to both positive and negative transitions of the second clock signal, and wherein the second gating circuit comprises third and fourth logic gates receiving the intermediate signal from the first and second logic gates, respectively, the third logic gate generating the respective data start signal responsive to receiving the intermediate signal from the first logic gate and a second enable pulse generated responsive to a positive transition of the second clock signal, the second logic gate generating the respective data start signal responsive to receiving the intermediate signal from the second logic circuit and a second enable pulse generated responsive to a negative transition of the second clock signal.

14. The memory device of claim 12 wherein the second clocking circuit generates second enable pulses responsive to both positive and negative transitions of the second clock signal, and wherein the second gating circuit comprises first and second logic gates receiving the intermediate signal, the first logic gate generating the respective data start signal responsive to receiving the intermediate signal and a second enable pulse generated responsive to a positive transition of the second clock signal, the second logic gate generating the respective data start signal responsive to receiving the intermediate signal and a second enable pulse generated responsive to a negative transition of the second clock signal.

15. The memory device of claim 12 wherein the first gating circuit comprises a latch circuit generating the intermediate signal until the latch circuit is reset, the latch circuit being reset responsive to the respective data start signal.

16. The memory device of claim 15 wherein the first clocking circuit generates first enable pulses responsive to both positive and negative transitions of the first clock signal, and wherein the first gating circuit comprises first and second logic gates receiving the first signal, the first logic gate generating the intermediate signal responsive to receiving the respective transfer initiate signal and a first enable pulse generated responsive to a positive transition of the first clock signal, the second logic gate generating the intermediate signal responsive to receiving the respective transfer initiate signal and a first enable pulse generated responsive to a negative transition of the first clock signal.

17. The memory device of claim 12 wherein the memory device comprises a dynamic random access memory device.

18. The memory device of claim 17 wherein the dynamic random access memory device comprises a packetized dynamic random access memory device.

19. A memory device, comprising:

a control circuit adapted to receive a command from an external source and generate control signals responsive thereto, the control circuit including a clock generator circuit adapted to receive an external clock signal and to generate an internal clock signal, a read transfer initiate signal, a write transfer initiate signal, a read data initiate signal, and a write data initiate signal, the timing of the read clock signal and the write clock signal being controlled by an external device;

a memory array coupled to the control circuit, the memory array having a plurality of memory cells adapted to store write data and output read data;

an addressing circuit coupled to the memory array and the control circuit, the addressing circuit adapted to receive addresses from an external source and select a memory cell in the memory array corresponding thereto;

a read data path having a read register coupled to the control circuit, the read register being adapted to couple read data from the memory array to an externally accessible terminal responsive to the read clock signal subsequent to the read data start signal being applied to a control input terminal;

a write data path having a write register coupled to the control circuit, the write register being adapted to couple write data from the externally accessible terminal to the memory array responsive to a write register clock signal subsequent to a write data start signal being applied to a control input terminal;

a first coupling circuit having an input terminal connected to the control circuit to receive the read transfer initiate signal and an output terminal connected to the control input terminal of the read register, the first coupling circuit comprising;

a first logic circuit coupled to receive the read transfer initiate signal and a first clock signal in the same clock domain as the internal clock signal, the first logic circuit generating a first intermediate signal responsive to each transition of the first clock signal subsequent to the read transfer signal being received unless a first reset signal is being applied to the first logic circuit; and

a second logic circuit coupled to the first logic circuit to receive the first intermediate signal and a second clock signal in the same domain as the read clock signal, the second logic circuit generating the read data start signal responsive to a transition of the second clock signal subsequent to the first intermediate signal being generated, the second logic circuit generating the first reset signal responsive to the read data start signal; and

a second coupling circuit having an input terminal connected to the control circuit to receive the write transfer initiate signal and an output terminal connected to the control input terminal of the write register, the second coupling circuit comprising;

a third logic circuit coupled to receive the write transfer initiate signal and a third clock signal in the same clock domain as the internal clock signal, the third logic circuit generating a second intermediate signal responsive to each transition of the third clock signal subsequent to the write transfer signal being received unless a second reset signal is being applied to the third logic circuit; and

a fourth logic circuit coupled to the third logic circuit to receive the second intermediate signal and a fourth clock signal in the same domain as the write clock signal, the fourth logic circuit generating the write data start signal responsive to a transition of the fourth clock signal subsequent to the second intermediate signal being generated, the fourth logic circuit generating the second reset signal responsive to the write data start signal.

20. The memory device of claim 19 wherein the first and third clock signals are identical to each other, and the second and fourth clock signals are identical to each other.

21. The memory device of claim 19 wherein the second and fourth logic circuits each comprises:

a clocking circuit generating enable pulses responsive to respective transitions of the respective second and fourth clock signals; and

a logic gate coupled to receive the respective intermediate signal from the respective first or third logic circuit and the enable pulses from the clocking circuit, the logic gate generating the respective data start signal responsive to receiving the respective intermediate signal from the respective first or third logic circuit and one of the enable pulses.

22. The memory device of claim 19 wherein the first and third logic circuits each comprises:

a first logic gate receiving a respective transfer initiate signal and a respective reset signal, the first logic gate generating an output signal responsive to the respective transfer initiate signal unless a respective reset signal is being applied to the first logic gate;

a clocking circuit generating enable pulses responsive to respective transitions of the respective first or third clock signal; and

a second logic gate coupled to receive the output signal of the first logic gate and the enable pulses from the clocking circuit, the second logic gate generating the respective intermediate signal responsive to receiving the output signal from the first logic gate and one of the enable pulses.

23. The memory device of claim 22 wherein the clocking circuit generates enable pulses responsive to both positive and negative transitions of the respective first or third clock signal, and wherein the second logic gate comprises first and second gating circuits receiving the output signal of the first logic gate, the first gating circuit generating the respective intermediate signal responsive to receiving the output signal from the first logic gate and an enable pulse generated responsive to a positive transition of the respective first or third clock signal, the second gating circuit generating the respective first or third intermediate signal responsive to receiving the output signal from the first logic gate and an enable pulse generated responsive to a negative transition of the respective first or third clock signal.

24. A computer system, comprising:

a processor having a processor bus;

an input device coupled to the processor through the processor bus and adapted to allow data to be entered into the computer system;

an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system;

a memory controller coupled to the processor through the processor bus; and

a memory device coupled to the processor through the processor bus, comprising;

a control circuit adapted to receive a command from the memory controller and generate control signals responsive thereto, the control circuit including a clock generator circuit adapted to receive an external clock signal and to generate an internal clock signal, a read transfer initiate signal, a write transfer initiate signal, a read data initiate signal, and a write data initiate signal, the timing of the read clock signal and the write clock signal being controlled by the memory controller;

a memory array coupled to the control circuit, the memory array having a plurality of memory cells adapted to store write data and output read data;

an addressing circuit coupled to the memory array and the control circuit, the addressing circuit adapted to receive addresses from the memory controller and select a memory cell in the memory array corresponding thereto;

a read data path having a read register coupled to the control circuit, the read register being adapted to couple read data from the memory array to an externally accessible responsive to the read clock signal subsequent to the read data start signal being applied to a control input terminal;

a write data path having a write register coupled to the control circuit, the write register being adapted to couple write data from the externally accessible terminal to the memory array responsive to a write register clock signal subsequent to a write data start signal being applied to a control input terminal;

a first coupling circuit having an input terminal connected to the control circuit to receive the read transfer initiate signal and an output terminal connected to the control input terminal of the read resister, the first coupling circuit comprising;

first logic circuit coupled to receive the read transfer initiate signal and a first clock signal in the same clock domain as the internal clock signal, the first logic circuit generating a first intermediate signal responsive to each transition of the first clock signal subsequent to the read transfer signal being received unless a first reset signal is being applied to the first logic circuit; and

a second logic circuit coupled to the first logic circuit to receive the first intermediate signal and a second clock signal in the same domain as the read clock signal, the second logic circuit generating the read data start signal responsive to a transition of the second clock signal subsequent to the first intermediate signal being generated, the second logic circuit generating the first reset signal responsive to the read data start signal; and

a second coupling circuit having an input terminal connected to the control circuit to receive the write transfer initiate signal and an output terminal connected to the control input terminal of the write register, the second coupling circuit comprising;

a third logic circuit coupled to receive the write transfer initiate signal and a third clock signal in the same clock domain as the internal clock signal, the third logic circuit generating a second intermediate signal responsive to each transition of the third clock signal subsequent to the write transfer signal being received unless a second reset signal is being applied to the third logic circuit; and

a fourth logic circuit coupled to the third logic circuit to receive the second intermediate signal and a fourth clock signal in the same domain as the write clock signal, the fourth logic circuit generating the write data start signal responsive to a transition of the fourth clock signal subsequent to the second intermediate signal being generated, the fourth logic circuit generating the second reset signal responsive to the write data start signal.

25. The memory device of claim 24 wherein the first and third clock signals are identical to each other, and the second and fourth clock signals are identical to each other.

26. The memory device of claim 24 wherein the second and fourth logic circuits each comprises:

a clocking circuit generating enable pulses responsive to respective transitions of the respective second and fourth clock signals; and

a logic gate coupled to receive the respective intermediate signal from the respective first or third logic circuit and the enable pulses from the clocking circuit, the logic gate generating the respective data start signal responsive to receiving the respective intermediate signal from the respective first or third logic circuit and one of the enable pulses.

27. The memory device of claim 24 wherein the first and third logic circuits each comprises:

a first logic gate receiving a respective transfer initiate signal and a respective reset signal, the first logic gate generating an output signal responsive to the respective transfer initiate signal unless a respective reset signal is being applied to the first logic gate;

a clocking circuit generating enable pulses responsive to respective transitions of the respective first or third clock signal; and

a second logic gate coupled to receive the output signal of the first logic gate and the enable pulses from the clocking circuit, the second logic gate generating the respective intermediate signal responsive to receiving the output signal from the first logic gate and one of the enable pulses.

28. The memory device of claim 27 wherein the clocking circuit generates enable pulses responsive to both positive and negative transitions of the respective first or third clock signal, and wherein the second logic gate comprises first and second gating circuits receiving the output signal of the first logic gate, the first gating circuit generating the respective intermediate signal responsive to receiving the output signal from the first logic gate and an enable pulse generated responsive to a positive transition of the respective first or third clock signal, the second gating circuit generating the respective first or third intermediate signal responsive to receiving the output signal from the first logic gate and an enable pulse generated responsive to a negative transition of the respective first or third clock signal.