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Method and apparatus for coupling signals between two circuits operating in different clock domains

  • US 6,000,022 A
  • Filed: 10/10/1997
  • Issued: 12/07/1999
  • Est. Priority Date: 10/10/1997
  • Status: Expired due to Term
First Claim
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1. An apparatus for applying a second signal to a second device operating in a second clock domain defined by a second clock signal responsive to a first signal received from a first device operating in a first clock domain defined by a first clock signal, the apparatus comprising:

  • a first logic circuit coupled to receive the first signal and the first clock signal, the first logic circuit generating an intermediate signal responsive to each transition of the first clock signal subsequent to the first signal being received unless a reset signal is being applied to the first logic circuit, the first logic circuit comprising;

    a third logic circuit to receive the first signal and the reset signal, the third logic circuit generating an output signal responsive to the first signal unless the reset signal is being applied to the third logic circuit;

    a clocking circuit generating enable pulses responsive to respective transitions of the first clock signal, the clocking circuit generating enable pulses responsive to both positive and negative transitions of the first clock signal; and

    a fourth logic circuit coupled to receive the output signal of the third logic circuit and the enable pulses from the first clocking circuit, the fourth logic circuit generating the intermediate signal responsive to receiving the output signal from the third logic circuit and one of the enable pulses, the fourth logic circuit comprising first and second gating circuit receiving the output signal of the third logic circuit, the first gating circuit generating the intermediate signal responsive to receiving the output signal from the third logic circuit and an enable pulse generated responsive to a positive transition of the first clock signal, the second logic gate generating the intermediate signal responsive to receiving the output signal from the third logic circuit and an enable pulse generated responsive to a negative transition of the first clock signal; and

    a second logic circuit coupled to the first logic circuit to receive the intermediate signal and the second clock signal, the second logic circuit generating the second signal responsive to a transition of the second clock signal subsequent to the intermediate signal being generated, the second logic circuit generating the reset signal responsive to the second signal.

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