Apparatus for randomly sampling instructions in a processor pipeline
First Claim
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1. An apparatus for sampling instructions in a processor pipeline of a system, the pipeline having a plurality of processing stages, comprising:
- means for fetching instructions into a first stage of the pipeline, the instructions being identified by additional fields indicating that they have been selected for sampling, the additional fields including a sample bit on each instruction in the pipeline;
means for identifying any one of the fetched instructions as a selected instruction;
means for sampling state information of the system while a particular selected instruction is in any stage of the pipeline, andmeans for informing software when the particular selected instruction leaves the pipeline so that the software can read any of the state information wherein the means for sampling and the means for informing software being activated by asserting of the sample bit in the selected instruction.
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Abstract
An apparatus is provided for sampling instructions in a processor pipeline of a system. The pipeline has a plurality of processing stages. The apparatus includes a fetch unit for fetching instructions into a first stage of the pipeline. Certain randomly selected instructions are identified, and state information of the system is sampled while a particular selected instruction is in any stage of the pipeline. Software is informed when the particular selected instruction leaves the pipeline so that the software can read any of the sampled state information.
181 Citations
29 Claims
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1. An apparatus for sampling instructions in a processor pipeline of a system, the pipeline having a plurality of processing stages, comprising:
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means for fetching instructions into a first stage of the pipeline, the instructions being identified by additional fields indicating that they have been selected for sampling, the additional fields including a sample bit on each instruction in the pipeline; means for identifying any one of the fetched instructions as a selected instruction; means for sampling state information of the system while a particular selected instruction is in any stage of the pipeline, and means for informing software when the particular selected instruction leaves the pipeline so that the software can read any of the state information wherein the means for sampling and the means for informing software being activated by asserting of the sample bit in the selected instruction. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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27. An apparatus for sampling instructions in a processor pipeline of a system, the pipeline having a plurality of processing stages, comprising:
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a fetch unit fetching instructions into a first stage of the pipeline, the instructions being identified by additional fields indicating that they have been selected for sampling, the additional fields including a sample bit on each instruction in the pipeline; a selection unit identifying any one of the fetched instructions as a selected instruction; a sampling unit sampling state information of the system while a particular selected instruction is in any stage of the pipeline; and an inform unit informing software when the particular selected instruction leaves the pipeline so that the software can read any of the state information wherein the sampling unit and the inform units being activated by asserting of the sample bit in the selected instruction.
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28. A method for sampling instructions in a processor pipeline of a system, the pipeline having a plurality of processing stages, comprising:
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fetching instructions into a first stage of the pipeline, the instructions being identified by additional fields indicating that they have been selected for sampling, the additional fields including a sample bit on each instruction in the pipeline; identifying any one of the fetched instructions as a selected instruction; sampling state information of the system while a particular selected instruction is in any stage of the pipeline; and informing software when the particular selected instruction leaves the pipeline so that the software can read any of the state information wherein sampling and informing software being activated by asserting of the sample bit in the selected instruction.
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29. A system, comprising:
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a memory storing instructions; a pipeline having a plurality of processing stages, comprising; a fetch unit fetching the instructions into a first stage of the pipeline, the instructions being identified by additional fields indicating that they have been selected for sampling, the additional fields including a sample bit on each instruction in the pipeline; a selection unit identifying any one of the fetched instructions as a selected instruction; a sampling unit sampling state information of the system while a particular selected instruction is in any stage of the pipeline; and an inform unit informing software when the particular selected instruction leaves the pipeline so that the software can read any of the state information; and an input/output unit to input and output data to and from the system wherein the sampling unit and the inform unit being activated by asserting of the sample bit in the selected instruction.
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Specification